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[209.132.180.67]) by mx.google.com with ESMTP id gq8si45972218pbc.50.2014.07.09.05.38.47; Wed, 09 Jul 2014 05:38:47 -0700 (PDT) Received-SPF: none (google.com: linux-kernel-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755755AbaGIMii (ORCPT + 28 others); Wed, 9 Jul 2014 08:38:38 -0400 Received: from comal.ext.ti.com ([198.47.26.152]:36368 "EHLO comal.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753456AbaGIMie (ORCPT ); Wed, 9 Jul 2014 08:38:34 -0400 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by comal.ext.ti.com (8.13.7/8.13.7) with ESMTP id s69Cbhiu005296; Wed, 9 Jul 2014 07:37:43 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id s69CbhI9031472; Wed, 9 Jul 2014 07:37:43 -0500 Received: from dlep33.itg.ti.com (157.170.170.75) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.174.1; Wed, 9 Jul 2014 07:37:43 -0500 Received: from localhost.localdomain (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep33.itg.ti.com (8.14.3/8.13.8) with ESMTP id s69CbX7j010057; Wed, 9 Jul 2014 07:37:40 -0500 From: Roger Quadros To: , CC: , , , , , , , , , Roger Quadros Subject: [RFC PATCH 02/10] mtd: nand: omap: Always use chip->ecc.steps for BCH sector count Date: Wed, 9 Jul 2014 15:37:22 +0300 Message-ID: <1404909450-11970-3-git-send-email-rogerq@ti.com> X-Mailer: git-send-email 1.8.3.2 In-Reply-To: <1404909450-11970-1-git-send-email-rogerq@ti.com> References: <1404909450-11970-1-git-send-email-rogerq@ti.com> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: rogerq@ti.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , Instead of hardcoding use the pre-calculated chip->ecc.steps for configuring number of sectors to process with the BCH algorithm. This also avoids unnecessary access to the ECC_CONFIG register in omap_calculate_ecc_bch(). Signed-off-by: Roger Quadros --- drivers/mtd/nand/omap2.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/nand/omap2.c b/drivers/mtd/nand/omap2.c index 5b8739c..6f3d7cd 100644 --- a/drivers/mtd/nand/omap2.c +++ b/drivers/mtd/nand/omap2.c @@ -1066,10 +1066,10 @@ static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode) unsigned int ecc_size1, ecc_size0; /* GPMC configurations for calculating ECC */ + nsectors = chip->ecc.steps; switch (ecc_opt) { case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: bch_type = 0; - nsectors = 1; if (mode == NAND_ECC_READ) { wr_mode = BCH_WRAPMODE_6; ecc_size0 = BCH_ECC_SIZE0; @@ -1082,7 +1082,6 @@ static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode) break; case OMAP_ECC_BCH4_CODE_HW: bch_type = 0; - nsectors = chip->ecc.steps; if (mode == NAND_ECC_READ) { wr_mode = BCH_WRAPMODE_1; ecc_size0 = BCH4R_ECC_SIZE0; @@ -1095,7 +1094,6 @@ static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode) break; case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: bch_type = 1; - nsectors = 1; if (mode == NAND_ECC_READ) { wr_mode = BCH_WRAPMODE_6; ecc_size0 = BCH_ECC_SIZE0; @@ -1108,7 +1106,6 @@ static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode) break; case OMAP_ECC_BCH8_CODE_HW: bch_type = 1; - nsectors = chip->ecc.steps; if (mode == NAND_ECC_READ) { wr_mode = BCH_WRAPMODE_1; ecc_size0 = BCH8R_ECC_SIZE0; @@ -1121,7 +1118,6 @@ static void __maybe_unused omap_enable_hwecc_bch(struct mtd_info *mtd, int mode) break; case OMAP_ECC_BCH16_CODE_HW: bch_type = 0x2; - nsectors = chip->ecc.steps; if (mode == NAND_ECC_READ) { wr_mode = 0x01; ecc_size0 = 52; /* ECC bits in nibbles per sector */ @@ -1176,6 +1172,7 @@ static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd, { struct omap_nand_info *info = container_of(mtd, struct omap_nand_info, mtd); + struct nand_chip *chip = mtd->priv; int eccbytes = info->nand.ecc.bytes; struct gpmc_nand_regs *gpmc_regs = &info->reg; u8 *ecc_code; @@ -1183,7 +1180,7 @@ static int __maybe_unused omap_calculate_ecc_bch(struct mtd_info *mtd, u32 val; int i, j; - nsectors = ((readl(info->reg.gpmc_ecc_config) >> 4) & 0x7) + 1; + nsectors = chip->ecc.steps; for (i = 0; i < nsectors; i++) { ecc_code = ecc_calc; switch (info->ecc_opt) {