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Fri, 23 May 2025 10:57:49 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 54NAvnvm027504; Fri, 23 May 2025 10:57:49 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-sartgarg-hyd.qualcomm.com [10.213.105.147]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 54NAvnjj027503; Fri, 23 May 2025 10:57:49 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2339771) id 82A24608B7B; Fri, 23 May 2025 16:27:48 +0530 (+0530) From: Sarthak Garg To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Adrian Hunter , Ulf Hansson Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, quic_cang@quicinc.com, quic_nguyenb@quicinc.com, quic_rampraka@quicinc.com, quic_pragalla@quicinc.com, quic_sayalil@quicinc.com, quic_nitirawa@quicinc.com, quic_bhaskarv@quicinc.com, Sarthak Garg Subject: [PATCH V2 1/3] mmc: sdhci-msm: Enable tuning for SDR50 mode for SD card Date: Fri, 23 May 2025 16:27:43 +0530 Message-Id: <20250523105745.6210-2-quic_sartgarg@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20250523105745.6210-1-quic_sartgarg@quicinc.com> References: <20250523105745.6210-1-quic_sartgarg@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: d-QxgDDI196Gnm2tMPklGDKNJ7MqE9-r X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTIzMDA5NiBTYWx0ZWRfX5xWs51S7gQU/ uqE/vimaP+h1aGPNO4fa3Ijp4ZFOBjEuOL/mpy6DKhB16drQl6DsE5e42VbSPosfO/AfHKDJb9r FpCjG01EPoXEIAKCqUymjMmwRg7pXhIYIj4NhVR8prZWoOYXb8xO7tWFCxpqYrbra1BwJ/jahFE 0clbckAlKm91BEwozgJZ8bRoZN7YZTPMs/b8T9rUcvMfBHrRO7tAIT8pWXVcP1BD2GrajbkRDGH N1cDzMj6cG0bSVguKYwcUrEML2luzCdzWF5uUeOy9IaeSj3TUEWh38F/bSdpoSOmm6D3wgt6R+G 2gyTJq3PHRQR1S9H/9kWN54JlPGqEBiQGsFk7SsgSFIF4lfy24eogdgQTS91Gt+CDoi96xEhQ/+ XBiJOPKAxKTFF9+kAXJBSAd0RABX6M2/wmTiADZlhYAnSK5tI23IBRmffuYMbXzjSZF6Aeaa X-Authority-Analysis: v=2.4 cv=fZOty1QF c=1 sm=1 tr=0 ts=683054b1 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=dt9VzEwgFbYA:10 a=COk6AnOGAAAA:8 a=nNGJRMnCL2qTWb1COHkA:9 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: d-QxgDDI196Gnm2tMPklGDKNJ7MqE9-r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-23_03,2025-05-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 mlxscore=0 adultscore=0 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 phishscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505230096 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: For Qualcomm SoCs which needs level shifter for SD card, extra delay is seen on receiver data path. To compensate this delay enable tuning for SDR50 mode for targets which has level shifter. SDHCI_SDR50_NEEDS_TUNING caps will be set for targets with level shifter on Qualcomm SOC's. Signed-off-by: Sarthak Garg --- drivers/mmc/host/sdhci-msm.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 66c0d1ba2a33..bf91cb96a0ea 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -81,6 +81,7 @@ #define CORE_IO_PAD_PWR_SWITCH_EN BIT(15) #define CORE_IO_PAD_PWR_SWITCH BIT(16) #define CORE_HC_SELECT_IN_EN BIT(18) +#define CORE_HC_SELECT_IN_SDR50 (4 << 19) #define CORE_HC_SELECT_IN_HS400 (6 << 19) #define CORE_HC_SELECT_IN_MASK (7 << 19) @@ -1133,6 +1134,10 @@ static bool sdhci_msm_is_tuning_needed(struct sdhci_host *host) { struct mmc_ios *ios = &host->mmc->ios; + if (ios->timing == MMC_TIMING_UHS_SDR50 && + host->flags & SDHCI_SDR50_NEEDS_TUNING) + return true; + /* * Tuning is required for SDR104, HS200 and HS400 cards and * if clock frequency is greater than 100MHz in these modes. @@ -1201,6 +1206,8 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) struct mmc_ios ios = host->mmc->ios; struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + const struct sdhci_msm_offset *msm_offset = msm_host->offset; + u32 config; if (!sdhci_msm_is_tuning_needed(host)) { msm_host->use_cdr = false; @@ -1217,6 +1224,14 @@ static int sdhci_msm_execute_tuning(struct mmc_host *mmc, u32 opcode) */ msm_host->tuning_done = 0; + if (ios.timing == MMC_TIMING_UHS_SDR50 && + host->flags & SDHCI_SDR50_NEEDS_TUNING) { + config = readl_relaxed(host->ioaddr + msm_offset->core_vendor_spec); + config &= ~CORE_HC_SELECT_IN_MASK; + config |= CORE_HC_SELECT_IN_EN | CORE_HC_SELECT_IN_SDR50; + writel_relaxed(config, host->ioaddr + msm_offset->core_vendor_spec); + } + /* * For HS400 tuning in HS200 timing requires: * - select MCLK/2 in VENDOR_SPEC