From patchwork Tue Jan 14 08:35:14 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yuanjie Yang X-Patchwork-Id: 857384 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 68BE11CDA0B; Tue, 14 Jan 2025 08:35:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736843738; cv=none; b=dfOwqWNNo1iQrm8uNuUUUfm3UIu6LxDpbJjyDc1Okvb3BY7wVsiqJqkiodwnaCIwSNx+7qZxjp2Q2IGJYMw5mzV2nepQZ6bPW+jcELLbnKmHUQh5I8yaSW1ctKa5RbAYEpnr3sGst70yFufB+G7h+wqUO8b66bqyioBXqEkT8eQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736843738; c=relaxed/simple; bh=llK2Ci8Pu326nE4Nqlz/LDhhlYmorj+NVwkboE7EhLA=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=hd2efz29vBBVvnS/MgJF8HGbVDTler4cziZ/HdwENCci8HOZL31pZQXzxeDuYPggad3hlX5sv+XPVZrPrGcRqyQKCPOQMPPMGUpGIQEBkML9oXZE8X13ptXxr6xa2K8vjdFVLRVqppW76XJg6zC3Mn6nGvJSctIN6qjZqHMnzF0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=mGrPIYcj; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="mGrPIYcj" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 50E7ZsXd028669; Tue, 14 Jan 2025 08:35:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:date:from:message-id:mime-version :subject:to; s=qcppdkim1; bh=wXFNUKxp//DwV0xEx+FQII9QWqbaPb0+uqw htASTzsg=; b=mGrPIYcjf+erjAwvjmoHT/+uKWo0e/TSzWfwmWo/tPXKs9H6hGQ wOUGJZlp4DYFbrzdcHBg0hC6D1aZb/e8mzPvY0ZidSx3Q2i9t5rJAddRKerf5+ie LQ+m8A14Aru7Sx2bPnU6OawOHNVzrogzoB8wkt5+FhWxDG12dBTMGp4IS9kyWVsO htjLRfE9DwAUKY5cTBxfa+UT6yKRl4dIvqDzvla+f7PIreDp2GIJIxV4y1YE5Xh+ NzQf4mW1RGF387XGjVhrqAl4vl0HQMjUZUTHjPj8Xi3CEsoAD3LSRHQ25JKw93YP f+65F9OFxpo+ibDnqP/yUENNVqJMp49evlA== Received: from aptaippmta02.qualcomm.com (tpe-colo-wan-fw-bordernet.qualcomm.com [103.229.16.4]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 445kp3845x-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 14 Jan 2025 08:35:30 +0000 (GMT) Received: from pps.filterd (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTP id 50E8ZQGv014149; Tue, 14 Jan 2025 08:35:26 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 4442beupx3-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 14 Jan 2025 08:35:26 +0000 Received: from APTAIPPMTA02.qualcomm.com (APTAIPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 50E8ZQGt014143; Tue, 14 Jan 2025 08:35:26 GMT Received: from cse-cd02-lnx.ap.qualcomm.com (cse-cd02-lnx.qualcomm.com [10.64.75.246]) by APTAIPPMTA02.qualcomm.com (PPS) with ESMTPS id 50E8ZPdO014142 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 14 Jan 2025 08:35:26 +0000 Received: by cse-cd02-lnx.ap.qualcomm.com (Postfix, from userid 4571896) id BDD8C1FFD; Tue, 14 Jan 2025 16:35:24 +0800 (CST) From: Yuanjie Yang To: adrian.hunter@intel.com, ulf.hansson@linaro.org, linux-arm-msm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, andersson@kernel.org Cc: quic_tingweiz@quicinc.com, quic_zhgao@quicinc.com, Yuanjie Yang Subject: [PATCH v4] mmc: sdhci-msm: Correctly set the load for the regulator Date: Tue, 14 Jan 2025 16:35:14 +0800 Message-Id: <20250114083514.258379-1-quic_yuanjiey@quicinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: uHD1jwH0l9OMFGMcI3ejqSGrJ4rLDkGp X-Proofpoint-ORIG-GUID: uHD1jwH0l9OMFGMcI3ejqSGrJ4rLDkGp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=999 bulkscore=0 clxscore=1015 spamscore=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 adultscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501140070 Qualcomm regulator supports two power supply modes: HPM and LPM. Currently, the sdhci-msm.c driver does not set the load to adjust the current for eMMC and SD. If the regulator dont't set correct load in LPM state, it will lead to the inability to properly initialize eMMC and SD. Set the correct regulator current for eMMC and SD to ensure that the device can work normally even when the regulator is in LPM. Signed-off-by: Yuanjie Yang --- Changes in v4: - Optimize msm_config_vmmc_regulator and msm_config_vqmmc_regulator code logic - Delete redundant return in msm_config_vmmc_regulator and msm_config_vqmmc_regulator - Rebase on tag: next-20250114 - Link to v3: https://lore.kernel.org/linux-arm-msm/20241226031845.2574669-1-quic_yuanjiey@quicinc.com/ Changes in v3: - Optimize the code logic and separate code for regulator vmmc and vqmmc - Rebase on tag: next-20241217 - Link to v2: https://lore.kernel.org/all/20241127095029.3918290-1-quic_yuanjiey@quicinc.com/ Changes in v2: - Add enum msm_reg_type to optimize the code - Delete redundant emmc type judgment - Link to v1: https://lore.kernel.org/linux-arm-msm/20241122075048.2006894-1-quic_yuanjiey@quicinc.com/ --- drivers/mmc/host/sdhci-msm.c | 53 ++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) base-commit: dab2734f8e9ecba609d66d1dd087a392a7774c04 diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 4610f067faca..e3d39311fdc7 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -134,9 +134,18 @@ /* Timeout value to avoid infinite waiting for pwr_irq */ #define MSM_PWR_IRQ_TIMEOUT_MS 5000 +/* Max load for eMMC Vdd supply */ +#define MMC_VMMC_MAX_LOAD_UA 570000 + /* Max load for eMMC Vdd-io supply */ #define MMC_VQMMC_MAX_LOAD_UA 325000 +/* Max load for SD Vdd supply */ +#define SD_VMMC_MAX_LOAD_UA 800000 + +/* Max load for SD Vdd-io supply */ +#define SD_VQMMC_MAX_LOAD_UA 22000 + #define msm_host_readl(msm_host, host, offset) \ msm_host->var_ops->msm_readl_relaxed(host, offset) @@ -1403,11 +1412,48 @@ static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level) return ret; } -static int sdhci_msm_set_vmmc(struct mmc_host *mmc) +static void msm_config_vmmc_regulator(struct mmc_host *mmc, bool hpm) +{ + int load; + + if (!hpm) + load = 0; + else if (!mmc->card) + load = max(MMC_VMMC_MAX_LOAD_UA, SD_VMMC_MAX_LOAD_UA); + else if (mmc_card_mmc(mmc->card)) + load = MMC_VMMC_MAX_LOAD_UA; + else if (mmc_card_sd(mmc->card)) + load = SD_VMMC_MAX_LOAD_UA; + else + return; + + regulator_set_load(mmc->supply.vmmc, load); +} + +static void msm_config_vqmmc_regulator(struct mmc_host *mmc, bool hpm) +{ + int load; + + if (!hpm) + load = 0; + else if (!mmc->card) + load = max(MMC_VQMMC_MAX_LOAD_UA, SD_VQMMC_MAX_LOAD_UA); + else if (mmc_card_sd(mmc->card)) + load = SD_VQMMC_MAX_LOAD_UA; + else + return; + + regulator_set_load(mmc->supply.vqmmc, load); +} + +static int sdhci_msm_set_vmmc(struct sdhci_msm_host *msm_host, + struct mmc_host *mmc, bool hpm) { if (IS_ERR(mmc->supply.vmmc)) return 0; + msm_config_vmmc_regulator(mmc, hpm); + return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd); } @@ -1420,6 +1466,8 @@ static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host, if (msm_host->vqmmc_enabled == level) return 0; + msm_config_vqmmc_regulator(mmc, level); + if (level) { /* Set the IO voltage regulator to default voltage level */ if (msm_host->caps_0 & CORE_3_0V_SUPPORT) @@ -1642,7 +1690,8 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) } if (pwr_state) { - ret = sdhci_msm_set_vmmc(mmc); + ret = sdhci_msm_set_vmmc(msm_host, mmc, + pwr_state & REQ_BUS_ON); if (!ret) ret = sdhci_msm_set_vqmmc(msm_host, mmc, pwr_state & REQ_BUS_ON);