From patchwork Fri Oct 4 10:23:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sricharan R X-Patchwork-Id: 833158 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 812CE15A851; Fri, 4 Oct 2024 10:25:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037505; cv=none; b=DDuPPEIAUa2PY9QBUfeSr9vwKj3Db9d9lsnMd28JaEhlf1Mnm4PUq4s4VC7WTxhndhMKErrh50Fs1fvj4QYYAL/mTuzlo96uxscfEhzlsxCLQzyfbMZudYR/fhIB/qc0GbwqZcbJK82o6eNTrMsN9q2dMiu+TltzS2M4YVlFJMs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1728037505; c=relaxed/simple; bh=fMfrpV/innGP3RffVC2QmLiNOHTUW4cnEBmyu3t3EIw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=SCnLyIqQpzeQst1Tv4g42vLeA5og9InIs/c/RcNGKn/A1ws13XL4r794SVXcLvMxReJb6IZ4YMYsG2SK2yr7LVwJVbaiTiZRmj/rG2l4l18Ned1a+4l0cNhvsvSasaiEdFEQneaCQYY/aJXLbgyJwOCMAthVYItPVMGa4bfrf4E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=GG/KX04T; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="GG/KX04T" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 4941xQAt019918; Fri, 4 Oct 2024 10:24:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= BMp4hs42n3EcV7J6yhokHWJvti+k5dDYAbAVplRUJ/g=; b=GG/KX04TaFXj6QiN a4a59HSNEDp6n12yjV1taTHPh3cf5Yag+WSvvH1oHzzHzVo+OFHhYS4ORa2raWDt J4A2T/yiBqddWttXwa2Uk/JmhnjS+ummw7avtKSQELk8zH9r9XO1F0sao5WgAZoo 2B/OavGfWDzMrAdk9k7UjcGheHxcbdLbOhpbNOHS4HYThbxzWz+79+5h7NoEc81Q 4DKSMS3Td6SN3bhNN/y1EeO1Gva4hmAt1VymFEbhwDCrweY84/sCWlgEQC9EeFVC 0cTQZ9V1bL/LfPwW64Ql6yPGR+lAxVcB6EDipOdhGXpSUXI1zdON875Ls4Rsm1ND gwxnRg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 42205d9sa8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 04 Oct 2024 10:24:51 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 494AOoVw004106 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 4 Oct 2024 10:24:50 GMT Received: from hu-srichara-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 4 Oct 2024 03:24:43 -0700 From: Sricharan R To: , , , , , , , , , , , , , , , , , , , , CC: , Subject: [PATCH V3 7/7] arm64: defconfig: Enable IPQ5424 RDP466 base configs Date: Fri, 4 Oct 2024 15:53:42 +0530 Message-ID: <20241004102342.2414317-8-quic_srichara@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241004102342.2414317-1-quic_srichara@quicinc.com> References: <20241004102342.2414317-1-quic_srichara@quicinc.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: mMekSFwN5HciHpG3QFMdOwGq_BBbWtff X-Proofpoint-ORIG-GUID: mMekSFwN5HciHpG3QFMdOwGq_BBbWtff X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 spamscore=0 phishscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 bulkscore=0 suspectscore=0 mlxlogscore=681 lowpriorityscore=0 adultscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410040075 From: Sricharan Ramabadhran Enable GCC, Pinctrl for Qualcomm's IPQ5424 SoC which is required to boot IPQ5424-RDP466 boards to a console shell. Signed-off-by: Sricharan Ramabadhran --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 5fdbfea7a5b2..107e46f5fa6a 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -596,6 +596,7 @@ CONFIG_PINCTRL_IMX93=y CONFIG_PINCTRL_MSM=y CONFIG_PINCTRL_IPQ5018=y CONFIG_PINCTRL_IPQ5332=y +CONFIG_PINCTRL_IPQ5424=y CONFIG_PINCTRL_IPQ8074=y CONFIG_PINCTRL_IPQ6018=y CONFIG_PINCTRL_IPQ9574=y @@ -1310,6 +1311,7 @@ CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_APSS_5018=y CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_5332=y +CONFIG_IPQ_GCC_5424=y CONFIG_IPQ_GCC_6018=y CONFIG_IPQ_GCC_8074=y CONFIG_IPQ_GCC_9574=y