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Mon, 6 May 2024 15:52:37 -0700 From: Krishna Yarlagadda To: , , , , , CC: , , , , , , , , , , , , , Subject: [RFC PATCH 06/11] i2c: tegra: split clock initialization code Date: Tue, 7 May 2024 04:21:34 +0530 Message-ID: <20240506225139.57647-7-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240506225139.57647-1-kyarlagadda@nvidia.com> References: <20240506225139.57647-1-kyarlagadda@nvidia.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37E:EE_|DS0PR12MB8416:EE_ X-MS-Office365-Filtering-Correlation-Id: 126af70d-8369-4306-2e3b-08dc6e1f4886 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|1800799015|36860700004|376005|82310400017|7416005; X-Microsoft-Antispam-Message-Info: 92ptHH9HaKuTXbIS0x/L73v5zyZQNI0B6B1zYiBCS3OQSdKexoWHB5uehcOdgFgYOHqcsdYHUERHctHnMtfbXH7vq1CfsOyew8wQkOw0CbqPQpabO2MBlGE5x5fxvldd2vdDN9vOnxoWzO0CK38XxkPANvkYTeFVmflGZdCcpGeFU8bvDCenLZp0ELq70SWy0nTrBl8bOAKEcyIJmMj3a6mkr+WgGGqv+hZYZ3KadocJ1Og4DHD4XV1+JhXpmiTbBezPEDEuT1/L+U5tKidjybC0mi0N4k2Gy+W8NC6s/FttZEjyP8lUDGl6fDXai3CZwYcV5MPmb536MJxweL5QXzmJP/5rnexWmiX2cpcxEdxG9yWELqe+S082rfZgKzCa/Wymg7BT4X11KDPnrtBmTQihjkacSumkIkqkHHS9VXxQGKyzY2eGnqtylJ8Bsqikjqkb/s++gOwQ1SXhzogmT/Kf+/kjuWmbaDMv1KWKuzMaCDE8uzL+4eKp8ZNxzuC/JoxRkDRLArDhpE7zjoXgPfJWln785jRLB0x9buVAlxgZUzShnPTWk6qoXRY9uEtgFH5jRTIZrGDrENMDmaNjDRXpsXONCnqQnJFwxVldHEVVeYL0M8xi0CoIQ/dtAUDwZU+UBJ7qCyD4Ppwch1QLSbWLgvISIuBlBIWGDHJQ0ZoxfIG2qP/XfMN+gK0WbiGIG9HC4siHyn2Qu2n0ZO5tAxbv8G/8rKdLdx5+HqHscDagnBTUomz23xTzkWXg6AVuvsIwXKm1LZHBdAp6CONu947J9MqXgMHWTWezqot2C4U0yjkkNg9FsafygCoyioOJ8t9SE9LnFgM9SY0uebYI/es4v6j8Ir1o+fFwKnG/sgl+vihlbMTOnjDt/6B2mWeXeh0snTBh9qJGTwD3MY9ByY/8Wljb0r1uWUcFYyFcgIpbuHEJWZVfbwLW+lY3RwSwa35IzpMSpLuZGiVYa5znoZPyFXcCPf0id6Da/6o7ducQysF3Lr7p+mDackodzJx5Jbn5Q2Cwv478nbSVQVQUe4thhylqv5FDrTlAqSxkeOvTkhPSfNa5zHRyvVupiKgTNeO4QQfFQ5IScZkQplRJhz/6s8YmbMDT8syCEs2l6ALTmkKsMnDoFu9Q2sU6WO5kwsp6mgV6GHNxY02CpedU8ueCQdfsvx0FgTlr+mK3BlqGHEN63WYo3jrWdVpXEBqli5Rmpyr5e+2VGH9NuQ2Aec/qYXj6zm4atOg1pbI/D7AKnM5ZPRtiVEzn/9jPG7kwwwDewLB4wZro08l/JM8dxcDWImcjF4dtDDuArxgB+3tzcx09Q4YrRtygRV+LxR4x4ilWVlAy8MmU3v/apEWruJ7oVfMFb4z6GjMV1sFzon8QfmUAZKuGAm2ftGTpJhls X-Forefront-Antispam-Report: CIP:216.228.118.232; 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Signed-off-by: Krishna Yarlagadda --- drivers/i2c/busses/i2c-tegra.c | 127 ++++++++++++++++++++------------- 1 file changed, 77 insertions(+), 50 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 85b31edc558d..b3dc2603db35 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -604,12 +604,83 @@ static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) return 0; } +static void tegra_i2c_set_clk_params(struct tegra_i2c_dev *i2c_dev) +{ + u32 val, clk_divisor, tsu_thd, tlow, thigh, non_hs_mode; + + switch (i2c_dev->timings.bus_freq_hz) { + case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: + default: + tlow = i2c_dev->hw->tlow_fast_fastplus_mode; + thigh = i2c_dev->hw->thigh_fast_fastplus_mode; + tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; + + if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) + non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; + else + non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; + break; + + case 0 ... I2C_MAX_STANDARD_MODE_FREQ: + tlow = i2c_dev->hw->tlow_std_mode; + thigh = i2c_dev->hw->thigh_std_mode; + tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; + non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; + break; + } + + /* make sure clock divisor programmed correctly */ + clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, + i2c_dev->hw->clk_divisor_hs_mode) | + FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); + i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); + + if (i2c_dev->hw->has_interface_timing_reg) { + val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | + FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); + i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); + } + + /* + * Configure setup and hold times only when tsu_thd is non-zero. + * Otherwise, preserve the chip default values. + */ + if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) + i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); +} + +static int tegra_i2c_set_div_clk(struct tegra_i2c_dev *i2c_dev) +{ + u32 clk_multiplier, tlow, thigh, non_hs_mode; + u32 timing, clk_divisor; + int err; + + timing = i2c_readl(i2c_dev, I2C_INTERFACE_TIMING_0); + + tlow = FIELD_GET(I2C_INTERFACE_TIMING_TLOW, timing); + thigh = FIELD_GET(I2C_INTERFACE_TIMING_THIGH, timing); + + clk_divisor = i2c_readl(i2c_dev, I2C_CLK_DIVISOR); + + non_hs_mode = FIELD_GET(I2C_CLK_DIVISOR_STD_FAST_MODE, clk_divisor); + + clk_multiplier = (thigh + tlow + 2) * (non_hs_mode + 1); + + err = clk_set_rate(i2c_dev->div_clk, + i2c_dev->timings.bus_freq_hz * clk_multiplier); + if (err) { + dev_err(i2c_dev->dev, "failed to set div_clk rate: %d\n", err); + return err; + } + + return 0; +} + static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) { - u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode; + u32 val; + int err; acpi_handle handle = ACPI_HANDLE(i2c_dev->dev); - struct i2c_timings *t = &i2c_dev->timings; - int err; /* * The reset shouldn't ever fail in practice. The failure will be a @@ -641,54 +712,10 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) if (IS_VI(i2c_dev)) tegra_i2c_vi_init(i2c_dev); - switch (t->bus_freq_hz) { - case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ: - default: - tlow = i2c_dev->hw->tlow_fast_fastplus_mode; - thigh = i2c_dev->hw->thigh_fast_fastplus_mode; - tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode; - - if (t->bus_freq_hz > I2C_MAX_FAST_MODE_FREQ) - non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode; - else - non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode; - break; - - case 0 ... I2C_MAX_STANDARD_MODE_FREQ: - tlow = i2c_dev->hw->tlow_std_mode; - thigh = i2c_dev->hw->thigh_std_mode; - tsu_thd = i2c_dev->hw->setup_hold_time_std_mode; - non_hs_mode = i2c_dev->hw->clk_divisor_std_mode; - break; - } - - /* make sure clock divisor programmed correctly */ - clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE, - i2c_dev->hw->clk_divisor_hs_mode) | - FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode); - i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR); - - if (i2c_dev->hw->has_interface_timing_reg) { - val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) | - FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow); - i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0); - } - - /* - * Configure setup and hold times only when tsu_thd is non-zero. - * Otherwise, preserve the chip default values. - */ - if (i2c_dev->hw->has_interface_timing_reg && tsu_thd) - i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1); - - clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1); - - err = clk_set_rate(i2c_dev->div_clk, - t->bus_freq_hz * clk_multiplier); - if (err) { - dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err); + tegra_i2c_set_clk_params(i2c_dev); + err = tegra_i2c_set_div_clk(i2c_dev); + if (err) return err; - } if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) { u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);