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Mon, 6 May 2024 15:52:54 -0700 From: Krishna Yarlagadda To: , , , , , CC: , , , , , , , , , , , , , Subject: [RFC PATCH 09/11] sdhci: dt-bindings: configuration settings Date: Tue, 7 May 2024 04:21:37 +0530 Message-ID: <20240506225139.57647-10-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240506225139.57647-1-kyarlagadda@nvidia.com> References: <20240506225139.57647-1-kyarlagadda@nvidia.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37E:EE_|DS0PR12MB8293:EE_ X-MS-Office365-Filtering-Correlation-Id: 257c4beb-e129-40cd-0f8a-08dc6e1f5282 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230031|376005|36860700004|1800799015|7416005|82310400017; X-Microsoft-Antispam-Message-Info: jf9e23SryRl1j7cNNnjnl+1qyMgm6dbbu4jj9fgZuvfc2Gql2dWtnoKQ6n/wfidgHfakWg0x5iIGBImPwbk6mJVQ2og2PXe5vqGlXLlIYrtZ9wpaygPJJuDuGBDM2x2EcLJr3ESBGfC/uZYnaM/dJE1MizJkp7sAwlUdLUsOS68iBcaO8w2QSXEHIBgRz9Nb9ycsYF699BWPS+iHP8WpxxSqd+p4j5pJCn+7r4PXHkYITyxoKOCSSW1kyE53ijxnyvaSkKK0kJyWlBX6Ix8+QYi4VDg4FVOFqPyCBZY82+JcIWYSHZKExDtr4hELPhJHfuwWS4DIiAuYGe2YBlFmwxxBtjJiPlt12R6uz6agPuIAP71lh2CXwV06hFAHPBcPuS/JB2TWFZYyPA7YXil++6IHPTBry71Y5PssufGldjnfvW6mAI73m23AYviYKYp3psZxE6SMYfNIWwAfFDiSUMw6Ebd1+8cttm4pXwVuERM0Pr9Xy57zrahXpcvkDRB/K6p4AaOJx44AlcqiQ1qNIQPaeTcHWidD0TD7OETT4gCFNnSE9eEHhJshLDQpMs6qMbKyySEn7wqDzKT5jefVbuE2qf4lQfogHg70Ry/nZsT3+VAM3ANVF/vDMQKIMtoJaVYXPgPFu6zb8CgLPxwDgKwgcem0ryllh/AW5it8TJZoJeOPkceeUt6vT7+wJ5Nw/KHSqrembXPMcTHlMQT4RZKstuXotg1L0Vc2/PFsa1Q7hxk7qbEjUy2fXHwYslc4Y4u0gZ6aSp1bEl0WzwmnMpQmG56OCHOO0K0zQr+2Aeq7Jp+ZtNNE1L1d5rc4PUm9l/rlkEFBZ0tJT/dmBpQab/MfbWreFS7yra1Smo6nKwjrdoBrFHcpmPoqy7LwhWBzaNJRmALge8g6cmwkbfXp9ivAdHWoByusoIxB0pR3D1h7Our+u5/FMh/K/odtj80zKBgD6x3gJwy8ssEfrgfsl7x+UCv87S0fOGWIMoarRlacpiDf3qYV3ZRChEUq0lqPlSjKklO6dZ1MZSVzoiqHyGYLZqw9mJ7VdK1MRH6X14tYkpB9lfnd75nLsPFoHKPFOzqq8ZDn1eC1NQ7azedyM28CfBBiOOq9tVTNLB1m+20zx8bIzh7Bku8bKdPOzFEox7zsJqvrPEkAtfUC4xVKu9VtqAMOLRU4IpTtDKaEQV3J0IGx6jOlrHzVs9KhafRs0iHKXeLbFXWVJRQZR5gDn5zU9BaDDsAEpdvPZq4jk9qkRnXoO47gBGVyD2Dt8bKI1BMnsSZ6KRl9IszDT7WS7am1agcH6G6kXVro+OHzr32pkrMjaDBimVw+n/WUz6OleKow3n3gP1NHtvqqkmEd6aMSjiTHZcXFpuRMJpaytKY= X-Forefront-Antispam-Report: CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE; SFS:(13230031)(376005)(36860700004)(1800799015)(7416005)(82310400017); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 May 2024 22:53:18.5658 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 257c4beb-e129-40cd-0f8a-08dc6e1f5282 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8293 SDHCI vendor tuning registers are configured using config setting framework. Document available config for Tegra SDHCI controllers. Signed-off-by: Krishna Yarlagadda --- .../bindings/mmc/nvidia,tegra20-sdhci.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml index 72987f0326a1..002bc1ffc156 100644 --- a/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.yaml @@ -177,6 +177,37 @@ properties: operates at a 1.8 V fixed I/O voltage. $ref: /schemas/types.yaml#/definitions/flag + config: + description: Config settings for SDHCI devices. + Config setting is the configuration based on chip/board/system + characterization on interface/controller settings. This is needed for + - making the controller internal configuration to better perform + - making the interface to work proper by setting drive strength, slew + rates etc + - making the low power leakage. + SDHCI has configuration based on device speed modes. + - common is set on all speeds and can be overridden by speed mode. + - List of speed modes and their config name + "default", /* MMC_TIMING_LEGACY */ + "sd-mmc-highspeed", /* MMC_TIMING_MMC_HS */ + "sd-mmc-highspeed", /* MMC_TIMING_SD_HS */ + "uhs-sdr12", /* MMC_TIMING_UHS_SDR12 */ + "uhs-sdr25", /* MMC_TIMING_UHS_SDR25 */ + "uhs-sdr50", /* MMC_TIMING_UHS_SDR50 */ + "uhs-sdr104", /* MMC_TIMING_UHS_SDR104 */ + "uhs-ddr52", /* MMC_TIMING_UHS_DDR50 */ + "uhs-ddr52", /* MMC_TIMING_MMC_DDR52 */ + "mmc-hs200", /* MMC_TIMING_MMC_HS200 */ + "mmc-hs400", /* MMC_TIMING_MMC_HS400 */ + type: object + unevaluatedProperties: true + properties: + nvidia,num-tuning-iter: + description: Specify DQS trim value for HS400 timing. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 0xffff + required: - compatible - reg @@ -278,6 +309,11 @@ examples: wp-gpios = <&gpio 57 0>; /* gpio PH1 */ power-gpios = <&gpio 155 0>; /* gpio PT3 */ bus-width = <8>; + config { + mmc-hs200 { + nvidia,num-tuning-iter = <0x2>; + }; + }; }; - |