From patchwork Thu Feb 22 19:17:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 775659 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7257C6AF93; Thu, 22 Feb 2024 19:17:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708629453; cv=none; b=GUnhhOjQmbM4f6lu6Q6pMs7vG52nSjBW17DKvUiQAlgTFsM1eAIYKaOazig/OOJRHaOIo2D0awau0z1mkFx26SiXUJQvSAINo9NSySHVoa6RJjIusGkO4hgnefgQG/73rIGC404G0E3wp+vUT3b8YKN/+LgqI+iPbCtbC7vmmjo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708629453; c=relaxed/simple; bh=FfzSgsSo035o7ryEhcxVsVQV058O7HGFw3aTLS/NzeI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jbq1Vpr1Dj0zZ4J5ojPdhvHXqt7kOMhBiz8e4gCAHQl9pVpew1eVhVvt1RZIff4iNQdFKLJwC7UBRWpYW3yfG9IynvLTCsV+8KFlubkFMsfJzfdIfsR7v2VsoxB0SU6u+SC6+FP00sJTlC2xbNGYJdrpcvZVAJDNWStpZT8Qh54= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=none smtp.helo=mx0b-0016f401.pphosted.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=R90OHXsV; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.helo=mx0b-0016f401.pphosted.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="R90OHXsV" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.24/8.17.1.24) with ESMTP id 41M9CMCY023744; Thu, 22 Feb 2024 11:17:29 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= pfpt0220; bh=HrWkWQ/kQqJLWulKnPDqvSBRFwR5PnOwvL6KFpRQKR4=; b=R90 OHXsVOxwziBdF3svqwAS3CamiSiN1+xFqnRetLsBUuKogtODL9wmegcTkJFotnBC bSAzizAZ9LNfblT2ON8qjD5X/C5Azj1vYs1v+QsSsX3bCyoRzjlZqnyktw/rGx3x lFxP/ZmcnBodyB4mGj1/ZIJc96uh/CRAH9AKe+T+Ihb3zMX9KGvvFqaY3Yfyubk+ hMlmEUGMVSYHamj5B9OIa/8060Vq7g1ymnsabYByhIv43F5OJg2Vqsy6dVEp+Lhk hebFV1IwTasyVsnWtzeYHZB+BFTsT6GuGqpaXfTzDcRwur2EtOW9NVqsnrph2coq Tp5JZ6i9y7Fyfll3gCQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3we3dwah9f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 22 Feb 2024 11:17:29 -0800 (PST) Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.48; Thu, 22 Feb 2024 11:17:28 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Thu, 22 Feb 2024 11:17:28 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id 022903F71A7; Thu, 22 Feb 2024 11:17:25 -0800 (PST) From: Elad Nachman To: , , , , CC: , Subject: [PATCH v3 2/2] mmc: xenon: add timeout for PHY init complete Date: Thu, 22 Feb 2024 21:17:14 +0200 Message-ID: <20240222191714.1216470-3-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240222191714.1216470-1-enachman@marvell.com> References: <20240222191714.1216470-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-GUID: DACLmym6ivxWFILuGJkemDOU3edTaUwM X-Proofpoint-ORIG-GUID: DACLmym6ivxWFILuGJkemDOU3edTaUwM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-22_15,2024-02-22_01,2023-05-22_02 From: Elad Nachman AC5X spec says PHY init complete bit must be polled until zero. We see cases in which timeout can take longer than the standard calculation on AC5X, which is expected following the spec comment above. According to the spec, we must wait as long as it takes for that bit to toggle on AC5X. Cap that with 100 delay loops so we won't get stuck forever. Fixes: 06c8b667ff5b ("mmc: sdhci-xenon: Add support to PHYs of Marvell Xenon SDHC") Acked-by: Adrian Hunter Cc: stable@vger.kernel.org Signed-off-by: Elad Nachman --- drivers/mmc/host/sdhci-xenon-phy.c | 29 ++++++++++++++++++++--------- 1 file changed, 20 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c index c3096230a969..cc9d28b75eb9 100644 --- a/drivers/mmc/host/sdhci-xenon-phy.c +++ b/drivers/mmc/host/sdhci-xenon-phy.c @@ -110,6 +110,8 @@ #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18) #define XENON_LOGIC_TIMING_VALUE 0x00AA8977 +#define XENON_MAX_PHY_TIMEOUT_LOOPS 100 + /* * List offset of PHY registers and some special register values * in eMMC PHY 5.0 or eMMC PHY 5.1 @@ -278,18 +280,27 @@ static int xenon_emmc_phy_init(struct sdhci_host *host) /* get the wait time */ wait /= clock; wait++; - /* wait for host eMMC PHY init completes */ - udelay(wait); - reg = sdhci_readl(host, phy_regs->timing_adj); - reg &= XENON_PHY_INITIALIZAION; - if (reg) { + /* + * AC5X spec says bit must be polled until zero. + * We see cases in which timeout can take longer + * than the standard calculation on AC5X, which is + * expected following the spec comment above. + * According to the spec, we must wait as long as + * it takes for that bit to toggle on AC5X. + * Cap that with 100 delay loops so we won't get + * stuck here forever: + */ + + ret = read_poll_timeout(sdhci_readl, reg, + !(reg & XENON_PHY_INITIALIZAION), + wait, XENON_MAX_PHY_TIMEOUT_LOOPS * wait, + false, host, phy_regs->timing_adj); + if (ret) dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n", - wait); - return -ETIMEDOUT; - } + wait * XENON_MAX_PHY_TIMEOUT_LOOPS); - return 0; + return ret; } #define ARMADA_3700_SOC_PAD_1_8V 0x1