From patchwork Fri Dec 8 20:21:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kamal Dasu X-Patchwork-Id: 752175 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=broadcom.com header.i=@broadcom.com header.b="JGOwng2k" Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C91761998 for ; Fri, 8 Dec 2023 12:21:31 -0800 (PST) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1d0c93b1173so19191675ad.2 for ; Fri, 08 Dec 2023 12:21:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; t=1702066891; x=1702671691; darn=vger.kernel.org; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=oYVGMasD9CVPZltjUGQRYY+db3ybFOvARtiIujjn4gQ=; b=JGOwng2kh3jt5QWLb376skLBkzlGb2xtl2tF71A/psyNfLLm30XjwuVDQx+NUUbpTW tTDhR0dAVpOWw76PdsZ+vkKdoG+e3bobj1WAW8Jnn5KhhPvhD+9jEi7jQEN+0ZAD9BWc lxwXBs3pMYEmq8WinUAsXfp/c1dVbInMgxZEc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1702066891; x=1702671691; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=oYVGMasD9CVPZltjUGQRYY+db3ybFOvARtiIujjn4gQ=; b=G69/YPif8LMmwIdgwuCwJaGss9JPcSRNMkd2y9j+QQUJca74Uf/kbDwBCllol9Cj6q h1Ye/3AipdhqUpUtlm9ioYTTUp3qn48EAMjZnroVLMp564yAL0eMT5yOP4OK/xn0On5p m1lBufXrpLVgFLA9mqzeU8Ep2fGpU2DLfSsbFGPVVw+MDnYLCwOu/qj5xHET/VklT/tJ fjy/o1sSsiT3gnNQYGOvxzQyAjLiZzmhuyT7uq2aU8k6kByjeSzcE9BDPvGQCLPp6txN 7OT4W/lpAuPF1e9BcuKwWGXwqrxU1EKWoIFAfSmsdSzG8Ol8r+KGsIDgEyI3Zgj2T9fF F08Q== X-Gm-Message-State: AOJu0Yy06dk0A/0XyF1YR6mTmMwNcQSlPHpzr6il8OmhH2PFKcQgb8C4 MroO/oE460DWOQSgpoxW5qDPHg== X-Google-Smtp-Source: AGHT+IH+nTOgLpRgnuZLYs5BQXNJBtNy9L5TktNY5AwoGQViw82oVKYXe5ga1sI8TztgRgy15ZE8Pw== X-Received: by 2002:a17:902:c20d:b0:1d0:3eac:e66 with SMTP id 13-20020a170902c20d00b001d03eac0e66mr574433pll.29.1702066891085; Fri, 08 Dec 2023 12:21:31 -0800 (PST) Received: from mail.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id v29-20020a63481d000000b005c19c586cb7sm1952127pga.33.2023.12.08.12.21.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Dec 2023 12:21:30 -0800 (PST) From: Kamal Dasu To: ulf.hansson@linaro.org, linux-kernel@vger.kernel.org, alcooperx@gmail.com, linux-arm-kernel@lists.infradead.org, adrian.hunter@intel.com, linux-mmc@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, devicetree@vger.kernel.org Cc: f.fainelli@gmail.com, bcm-kernel-feedback-list@broadcom.com, Kamal Dasu Subject: [PATCH 2/2] mmc: add new sdhci reset sequence for brcm 74165b0 Date: Fri, 8 Dec 2023 15:21:08 -0500 Message-Id: <20231208202108.7468-2-kamal.dasu@broadcom.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231208202108.7468-1-kamal.dasu@broadcom.com> References: <20231208202108.7468-1-kamal.dasu@broadcom.com> Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: From: Kamal Dasu 74165b0 shall use a new sdio controller core version which requires a different reset sequence. For core reset we use sdhci_reset. For CMD and/or DATA reset added a new function to also enable SDCHI clocks SDHCI_CLOCK_CARD_EN SDHCI_CLOCK_INT_EN along with the SDHCI_RESET_CMD and/or SDHCI_RESET_DATA fields. Signed-off-by: Kamal Dasu --- drivers/mmc/host/sdhci-brcmstb.c | 69 +++++++++++++++++++++++++++++--- 1 file changed, 64 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci-brcmstb.c b/drivers/mmc/host/sdhci-brcmstb.c index c23251bb95f3..3fac471b5b5d 100644 --- a/drivers/mmc/host/sdhci-brcmstb.c +++ b/drivers/mmc/host/sdhci-brcmstb.c @@ -44,8 +44,13 @@ struct brcmstb_match_priv { static inline void enable_clock_gating(struct sdhci_host *host) { + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); u32 reg; + if (!(priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK)) + return; + reg = sdhci_readl(host, SDHCI_VENDOR); reg |= SDHCI_VENDOR_GATE_SDCLK_EN; sdhci_writel(host, reg, SDHCI_VENDOR); @@ -53,14 +58,54 @@ static inline void enable_clock_gating(struct sdhci_host *host) static void brcmstb_reset(struct sdhci_host *host, u8 mask) { - struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); - struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); - sdhci_and_cqhci_reset(host, mask); /* Reset will clear this, so re-enable it */ - if (priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK) - enable_clock_gating(host); + enable_clock_gating(host); +} + +static void brcmstb_sdhci_reset_cmd_data(struct sdhci_host *host, u8 mask) +{ + ktime_t timeout; + u32 reg; + u32 new_mask = (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) << 24; + + new_mask |= SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN; + reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); + sdhci_writel(host, reg | new_mask, SDHCI_CLOCK_CONTROL); + + /* Wait max 10 ms */ + timeout = ktime_add_ms(ktime_get(), 10); + + /* hw clears the bit when it's done */ + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + if (!(sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask)) + break; + if (timedout) { + pr_err("%s: Reset 0x%x never completed.\n", + mmc_hostname(host->mmc), (int)mask); + sdhci_err_stats_inc(host, CTRL_TIMEOUT); + sdhci_dumpregs(host); + return; + } + udelay(10); + } +} + +static void brcmstb_reset_74165b0(struct sdhci_host *host, u8 mask) +{ + /* take care of RESET_ALL as usual */ + if (mask & SDHCI_RESET_ALL) + sdhci_and_cqhci_reset(host, SDHCI_RESET_ALL); + + /* cmd and/or data treated differently on this core */ + if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) + brcmstb_sdhci_reset_cmd_data(host, mask); + + /* Reset will clear this, so re-enable it */ + enable_clock_gating(host); } static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) @@ -162,6 +207,13 @@ static struct sdhci_ops sdhci_brcmstb_ops_7216 = { .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, }; +static const struct sdhci_ops sdhci_brcmstb_ops_74165b0 = { + .set_clock = sdhci_brcmstb_set_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = brcmstb_reset_74165b0, + .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, +}; + static struct brcmstb_match_priv match_priv_7425 = { .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, @@ -179,10 +231,17 @@ static const struct brcmstb_match_priv match_priv_7216 = { .ops = &sdhci_brcmstb_ops_7216, }; +static const struct brcmstb_match_priv match_priv_74165b0 = { + .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, + .hs400es = sdhci_brcmstb_hs400es, + .ops = &sdhci_brcmstb_ops_74165b0, +}; + static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = { { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, + { .compatible = "brcm,bcm74165b0-sdhci", .data = &match_priv_74165b0 }, {}, };