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([82.78.167.145]) by smtp.gmail.com with ESMTPSA id f21-20020a05640214d500b0051e22660835sm5422415edx.46.2023.09.11.21.53.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Sep 2023 21:53:15 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: geert+renesas@glider.be, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, ulf.hansson@linaro.org, linus.walleij@linaro.org, gregkh@linuxfoundation.org, jirislaby@kernel.org, magnus.damm@gmail.com, catalin.marinas@arm.com, will@kernel.org, prabhakar.mahadev-lad.rj@bp.renesas.com, biju.das.jz@bp.renesas.com, quic_bjorande@quicinc.com, arnd@arndb.de, konrad.dybcio@linaro.org, neil.armstrong@linaro.org, nfraprado@collabora.com, rafal@milecki.pl, wsa+renesas@sang-engineering.com Cc: linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Claudiu Beznea Subject: [PATCH 29/37] dt-bindings: pinctrl: renesas: document RZ/G3S SoC Date: Tue, 12 Sep 2023 07:51:49 +0300 Message-Id: <20230912045157.177966-30-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> References: <20230912045157.177966-1-claudiu.beznea.uj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: Claudiu Beznea Add documentation for pin controller found on RZ/G3S (R9A08G045) SoC. Compared with RZ/G2{L,UL} RZ/G3S has 82 general-purpose IOs, no slew rate and output impedance support and more values for drive strength which needs to be expressed in microamp. Signed-off-by: Claudiu Beznea --- .../pinctrl/renesas,rzg2l-pinctrl.yaml | 26 +++++++++++++++---- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 145c5442f268..079e5be69330 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -25,6 +25,7 @@ properties: - enum: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} + - renesas,r9a08g045-pinctrl # RZ/G3S - items: - enum: @@ -77,6 +78,26 @@ additionalProperties: - $ref: pincfg-node.yaml# - $ref: pinmux-node.yaml# + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a08g045-pinctrl + then: + properties: + drive-strength-microamp: + enum: [ 1900, 2200, 4000, 4400, 4500, 4700, 5200, 5300, 5700, + 5800, 6000, 6050, 6100, 6550, 6800, 7000, 8000, 9000, + 10000 ] + else: + properties: + drive-strength: + enum: [ 2, 4, 8, 12 ] + output-impedance-ohms: + enum: [ 33, 50, 66, 100 ] + slew-rate: true + description: Pin controller client devices use pin configuration subnodes (children and grandchildren) for desired pin configuration. @@ -89,14 +110,9 @@ additionalProperties: alternate function configuration number using the RZG2L_PORT_PINMUX() helper macro in . pins: true - drive-strength: - enum: [ 2, 4, 8, 12 ] - output-impedance-ohms: - enum: [ 33, 50, 66, 100 ] power-source: description: I/O voltage in millivolt. enum: [ 1800, 2500, 3300 ] - slew-rate: true gpio-hog: true gpios: true input-enable: true