From patchwork Fri Aug 11 10:07:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gatien CHEVALLIER X-Patchwork-Id: 713042 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AB631C04FDF for ; Fri, 11 Aug 2023 10:12:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235835AbjHKKMe (ORCPT ); Fri, 11 Aug 2023 06:12:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35040 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235691AbjHKKMQ (ORCPT ); Fri, 11 Aug 2023 06:12:16 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8BF630F8; Fri, 11 Aug 2023 03:10:40 -0700 (PDT) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 37B87te2007813; Fri, 11 Aug 2023 12:10:08 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=Z9RHAsA52emjB/XR0eL1RL+AuLIHvu4a8YPaJiSvHi4=; b=Um /LQ+RFnJpy8V20c0OUMajl4xJYsX7xYdpikpcyBzqhFpDapJGbph5aGscyxsIwwj 1sU7aqL/KnnNbqzEYFMJGHylWQS1g3AIffx5bwYGRxYL9PnnxXFa+gTbAL1O0KDL gLFoe5rjoEzuxDDQwuzBeFiHtzDUp71bXQPmgZT1uE/UFd+QyEpFKKGMfSmn1Z8d Z3wjMoIHkbmvtyWuDXLNUHBgMtz9PqhqzFGVOhN7eLFQ1pq6u+evMWF575i4VeE1 6980q/feu6WeW/wuG8nzhC/GnJqReKxLl2HWBzhbLz/b16WfSgzXSr0cYY7x9zCr Yv4NjhwHu/3LTExs3NaA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3sdh74grcp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 11 Aug 2023 12:10:08 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B8D2110004F; Fri, 11 Aug 2023 12:10:07 +0200 (CEST) Received: from Webmail-eu.st.com (eqndag1node4.st.com [10.75.129.133]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A24EE2138F4; Fri, 11 Aug 2023 12:10:07 +0200 (CEST) Received: from localhost (10.201.21.121) by EQNDAG1NODE4.st.com (10.75.129.133) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 11 Aug 2023 12:10:07 +0200 From: Gatien Chevallier To: , , , , , , , , , , , , , , , , , , , , , , , , , Frank Rowand , CC: , , , , , , , , , , , , , , , , Gatien Chevallier Subject: [PATCH v4 08/11] arm64: dts: st: add RIFSC as a domain controller for STM32MP25x boards Date: Fri, 11 Aug 2023 12:07:28 +0200 Message-ID: <20230811100731.108145-9-gatien.chevallier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230811100731.108145-1-gatien.chevallier@foss.st.com> References: <20230811100731.108145-1-gatien.chevallier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.121] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To EQNDAG1NODE4.st.com (10.75.129.133) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-08-10_20,2023-08-10_01,2023-05-22_02 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org RIFSC is a firewall controller. Change its compatible so that is matches the documentation and reference RIFSC as a feature-domain-controller. Signed-off-by: Gatien Chevallier --- Changes in V2: - Fix rifsc node name - Move the "ranges" property under the "feature-domains" one arch/arm64/boot/dts/st/stm32mp251.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5268a4321841..cb084381e4cd 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -105,11 +105,13 @@ soc@0 { interrupt-parent = <&intc>; ranges = <0x0 0x0 0x0 0x80000000>; - rifsc: rifsc-bus@42080000 { - compatible = "simple-bus"; + rifsc: bus@42080000 { + compatible = "st,stm32mp25-rifsc"; reg = <0x42080000 0x1000>; #address-cells = <1>; #size-cells = <1>; + feature-domain-controller; + #feature-domain-cells = <1>; ranges; usart2: serial@400e0000 { @@ -117,6 +119,7 @@ usart2: serial@400e0000 { reg = <0x400e0000 0x400>; interrupts = ; clocks = <&ck_flexgen_08>; + feature-domains = <&rifsc 32>; status = "disabled"; }; };