From patchwork Fri Oct 14 11:45:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Shih X-Patchwork-Id: 615177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4203DC4332F for ; Fri, 14 Oct 2022 11:48:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229806AbiJNLsk (ORCPT ); Fri, 14 Oct 2022 07:48:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46490 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229709AbiJNLsW (ORCPT ); Fri, 14 Oct 2022 07:48:22 -0400 Received: from mail-pg1-x534.google.com (mail-pg1-x534.google.com [IPv6:2607:f8b0:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D21923EB2; Fri, 14 Oct 2022 04:48:00 -0700 (PDT) Received: by mail-pg1-x534.google.com with SMTP id 128so4113487pga.1; Fri, 14 Oct 2022 04:48:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h5ky6yRKLirOgAuzcb87q4FCsZ9Aux469YNihh1WRPk=; b=a0MQ+tiKfkhQQkR64P/I2X2M+Di/pU2Qf8MZdJZEUKK4sHspYJTYEtHCc598A8thjo Ke7DXD3dce+oIQtLoN7qSn/XRZpaqb4d8ndiDC1+v1XxF8tjrmdvzC1HzXZkAno9Jzua bi5+0yJ9dkRtLwpwwEkqoufSjpJPoYAUMN1B9kwQTJBWNaXW3uE74XBiTgBmoNjULHCW S0z5EF3S0hVvYhM9OUURvuSARyJw/csCpf8q0fZ8AOORnLCfj1DiGTM6LFdYa7I+I3Ya mmuY6TjKYzTyNK9LIXKeM6jvVZgF8AFjmibcmcpOXrVGLLfG5vJlh10LeidytqifVPog dwKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h5ky6yRKLirOgAuzcb87q4FCsZ9Aux469YNihh1WRPk=; b=kcicGxJF5/mOTH9FNAybkFSEgMX9n7P41SemSdFhkF7x/aLn1KMRKJcyAssWcgrcfr yrlGZ1rdpKb2tzZBNIU+zRbjjT/z1A4cGIb52HRbie6PTmvzuYcCvyG0ZTp08ng6cO43 cUzcwtQ4ogiKeoyGfmwP6sBIQ0uPhyCZDVCjM2tu0AGZbjnKpMobNxRL6tsgu+hpzM3V kW/HJYagUlxHemL3kI2Jt178+kwWD8LVsA4ivXYZGDMRRTt444nLodojT7g+RAV+O5K/ PVbdNoBm6Yskch2Jcsjc1d580B6Fl5fHvYx4Peg26qgrISITzetBe/Ey8LpS+HtyzmBl IdvQ== X-Gm-Message-State: ACrzQf1evJWo3/lHD7HzKNW7mMI9sNLERJG2BCPjPD02dCl8s/HlreQb 63u2eyLX3hnbqUjVp4s2YSVKUSg6CUHJEA== X-Google-Smtp-Source: AMsMyM6+p9/hfoQMMCnl2Yho4F6a7OJ0NuDVN3I+C69W9p5fohVI5HVY+NUGGhoOak9mSf22e99tcg== X-Received: by 2002:a05:6a00:f03:b0:563:210a:5ffb with SMTP id cr3-20020a056a000f0300b00563210a5ffbmr4763880pfb.70.1665748070824; Fri, 14 Oct 2022 04:47:50 -0700 (PDT) Received: from localhost.localdomain (2001-b400-e282-2aaa-c1aa-06c8-0e68-c5ee.emome-ip6.hinet.net. [2001:b400:e282:2aaa:c1aa:6c8:e68:c5ee]) by smtp.gmail.com with ESMTPSA id x8-20020a170902ec8800b001746f66244asm1606678plg.18.2022.10.14.04.47.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 14 Oct 2022 04:47:50 -0700 (PDT) From: Victor Shih X-Google-Original-From: Victor Shih To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, benchuanggli@gmail.com, HL.Liu@genesyslogic.com.tw, Greg.tu@genesyslogic.com.tw, takahiro.akashi@linaro.org, dlunev@chromium.org, Victor Shih , Ben Chuang Subject: [PATCH V5 14/26] mmc: sdhci-uhs2: add set_timeout() Date: Fri, 14 Oct 2022 19:45:49 +0800 Message-Id: <20221014114601.15594-15-victor.shih@genesyslogic.com.tw> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221014114601.15594-1-victor.shih@genesyslogic.com.tw> References: <20221014114601.15594-1-victor.shih@genesyslogic.com.tw> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org From: AKASHI Takahiro This is a UHS-II version of sdhci's set_timeout() operation. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/host/sdhci-uhs2.c | 85 +++++++++++++++++++++++++++++++++++ drivers/mmc/host/sdhci-uhs2.h | 1 + 2 files changed, 86 insertions(+) diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 4dc3e904d7d2..2b90e5308764 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -196,6 +196,91 @@ void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, } EXPORT_SYMBOL_GPL(sdhci_uhs2_set_power); +static u8 sdhci_calc_timeout_uhs2(struct sdhci_host *host, u8 *cmd_res, + u8 *dead_lock) +{ + u8 count; + unsigned int cmd_res_timeout, dead_lock_timeout, current_timeout; + + /* + * If the host controller provides us with an incorrect timeout + * value, just skip the check and use 0xE. The hardware may take + * longer to time out, but that's much better than having a too-short + * timeout value. + */ + if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) { + *cmd_res = 0xE; + *dead_lock = 0xE; + return 0xE; + } + + /* timeout in us */ + cmd_res_timeout = 5 * 1000; + dead_lock_timeout = 1 * 1000 * 1000; + + /* + * Figure out needed cycles. + * We do this in steps in order to fit inside a 32 bit int. + * The first step is the minimum timeout, which will have a + * minimum resolution of 6 bits: + * (1) 2^13*1000 > 2^22, + * (2) host->timeout_clk < 2^16 + * => + * (1) / (2) > 2^6 + */ + count = 0; + current_timeout = (1 << 13) * 1000 / host->timeout_clk; + while (current_timeout < cmd_res_timeout) { + count++; + current_timeout <<= 1; + if (count >= 0xF) + break; + } + + if (count >= 0xF) { + DBG("%s: Too large timeout 0x%x requested for CMD_RES!\n", + mmc_hostname(host->mmc), count); + count = 0xE; + } + *cmd_res = count; + + count = 0; + current_timeout = (1 << 13) * 1000 / host->timeout_clk; + while (current_timeout < dead_lock_timeout) { + count++; + current_timeout <<= 1; + if (count >= 0xF) + break; + } + + if (count >= 0xF) { + DBG("%s: Too large timeout 0x%x requested for DEADLOCK!\n", + mmc_hostname(host->mmc), count); + count = 0xE; + } + *dead_lock = count; + + return count; +} + +static void __sdhci_uhs2_set_timeout(struct sdhci_host *host) +{ + u8 cmd_res, dead_lock; + + sdhci_calc_timeout_uhs2(host, &cmd_res, &dead_lock); + cmd_res |= dead_lock << SDHCI_UHS2_TIMER_CTRL_DEADLOCK_SHIFT; + sdhci_writeb(host, cmd_res, SDHCI_UHS2_TIMER_CTRL); +} + +void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) +{ + __sdhci_set_timeout(host, cmd); + + if (host->mmc->flags & MMC_UHS2_SUPPORT) + __sdhci_uhs2_set_timeout(host); +} +EXPORT_SYMBOL_GPL(sdhci_uhs2_set_timeout); + /*****************************************************************************\ * * * MMC callbacks * diff --git a/drivers/mmc/host/sdhci-uhs2.h b/drivers/mmc/host/sdhci-uhs2.h index 3179915f7f79..5ea235b14108 100644 --- a/drivers/mmc/host/sdhci-uhs2.h +++ b/drivers/mmc/host/sdhci-uhs2.h @@ -215,5 +215,6 @@ bool sdhci_uhs2_mode(struct sdhci_host *host); void sdhci_uhs2_reset(struct sdhci_host *host, u16 mask); void sdhci_uhs2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd); +void sdhci_uhs2_set_timeout(struct sdhci_host *host, struct mmc_command *cmd); #endif /* __SDHCI_UHS2_H */