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Tue, 19 Apr 2022 11:35:34 +0000 From: Abel Vesa To: Rob Herring , Krzysztof Kozlowski , Ulf Hansson , Shawn Guo , Sascha Hauer Cc: Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-mmc@vger.kernel.org, , linux-arm-kernel@lists.infradead.org, Jacky Bai Subject: [PATCH v8 04/13] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl Date: Tue, 19 Apr 2022 14:35:07 +0300 Message-Id: <20220419113516.1827863-5-abel.vesa@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220419113516.1827863-1-abel.vesa@nxp.com> References: <20220419113516.1827863-1-abel.vesa@nxp.com> X-ClientProxiedBy: VE1PR03CA0026.eurprd03.prod.outlook.com (2603:10a6:803:118::15) To VI1PR04MB4688.eurprd04.prod.outlook.com (2603:10a6:803:6a::30) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 21d203f5-65ef-4696-a2ff-08da21f8b777 X-MS-TrafficTypeDiagnostic: VI1PR04MB3054:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Additional db pmu is added compared to i.MX8QXP. Signed-off-by: Jacky Bai Signed-off-by: Abel Vesa --- .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi new file mode 100644 index 000000000000..8a91eb33b4ef --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +&ddr_subsys { + db_ipg_clk: clock-db-ipg@0 { + compatible = "fixed-clock"; + reg = <0 0>; + #clock-cells = <0>; + clock-frequency = <456000000>; + clock-output-names = "db_ipg_clk"; + }; + + db_pmu0: db-pmu@5ca40000 { + compatible = "fsl,imx8dxl-db-pmu"; + reg = <0x5ca40000 0x10000>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&db_pmu0_lpcg IMX_LPCG_CLK_0>, + <&db_pmu0_lpcg IMX_LPCG_CLK_1>; + clock-names = "ipg", "cnt"; + power-domains = <&pd IMX_SC_R_PERF>; + }; + + db_pmu0_lpcg: clock-controller@5cae0000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5cae0000 0x10000>; + #clock-cells = <1>; + clocks = <&db_ipg_clk>, <&db_ipg_clk>; + clock-indices = , + ; + clock-output-names = "perf_lpcg_cnt_clk", + "perf_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_PERF>; + }; +};