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Mon, 29 Nov 2021 11:10:53 +0000 From: Prathamesh Shete To: , , , , , , , CC: , Subject: [PATCH] mmc: sdhci-tegra: Add support to enumerate in HS400ES mode Date: Mon, 29 Nov 2021 16:40:47 +0530 Message-ID: <20211129111047.5299-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e7863385-f600-4c5c-c684-08d9b328eb2e X-MS-TrafficTypeDiagnostic: BN8PR12MB2883: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2201; X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aUQlhObVwHqMgetAF47ZmGibG9pzekHPfmB9KCX8Yk8Hj3LAPJZtV8PAsemi0qKu/zAQqMM7U8txwpAfwE2q2ngzzcmwu7IC1h/21Fpb+H1Lz5gg2s1QdcZRwl1I9AcVK3iNEncgCOmRSHl/Klr1xtH2W7zGNThCF9pvFhBTndNIvGuWWohcQVYZAlz5loid6gu/xJgB6jQrDzvooDSy1lejMeONTAXkucaPpLziz2pKbivSmBdwFuDa45fjP0uXEoOBmuht9vpwTMz33e1439YYw8nuLp+Rb/CkcOPLo2cqdOc9VoGu55Ai+iS+Hujpazz7bYNcnK83AxQoWvwWW6npWuraOd9FGnRaAYRAQpcqRoiDaLnVq4zn90XaHcC8CHA6nOC5S2a3z3ldliElwTkN1Cr6m6dSY2ghL/xhthNu2SVDEjTQ4A+O/5//fEw/ySE91H78pVo87BLegJCeXTptScjFqcCkMpfXPV2BXA38fVlE4e1Ffcl4bQN7Y5r9IO5vPlXlJ5yyi3gLhu74+3t1iSdH2XWOftptbcZKMYK1bX+bxeKMo0WfWSi4ChfUMTtTtW6nZrTGwYkti29VCvsp/tHMVRZe6P7aqyTwI5CIrtKhnBtskmrDQC6sei8PgrgmZW8SuSLIV/F9Eqxd2o88cacxy2xg3JGETVxDcDyGP/BnVlZFE0wr9F5eDX/WC67cjBt879nmfcSbycdsoQ== X-Forefront-Antispam-Report: CIP:216.228.112.36; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid05.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(36756003)(2906002)(1076003)(83380400001)(5660300002)(8676002)(70586007)(426003)(336012)(107886003)(70206006)(6666004)(8936002)(110136005)(316002)(26005)(54906003)(86362001)(186003)(36860700001)(82310400004)(7696005)(7636003)(2616005)(4326008)(47076005)(356005)(508600001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Nov 2021 11:10:57.4241 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e7863385-f600-4c5c-c684-08d9b328eb2e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN8PR12MB2883 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org When CMD13 is sent after switching to HS400 mode, the bus is operating at either MMC_HIGH_26_MAX_DTR or MMC_HIGH_52_MAX_DTR. To meet Tegra SDHCI requirement at HS400 mode, force SDHCI interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host controller CAR clock and the interface clock are rate matched. Signed-off-by: Prathamesh Shete --- drivers/mmc/host/sdhci-tegra.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 387ce9cdbd7c..d800396d1112 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -123,6 +123,8 @@ SDHCI_TRNS_BLK_CNT_EN | \ SDHCI_TRNS_DMA) +static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock); + struct sdhci_tegra_soc_data { const struct sdhci_pltfm_data *pdata; u64 dma_mask; @@ -369,6 +371,16 @@ static void tegra_sdhci_hs400_enhanced_strobe(struct mmc_host *mmc, sdhci_writel(host, val, SDHCI_TEGRA_VENDOR_SYS_SW_CTRL); + /* + * When CMD13 is sent after switching to HS400 mode, the bus + * is operating at either MMC_HIGH_26_MAX_DTR or + * MMC_HIGH_52_MAX_DTR. + * To meet Tegra SDHCI requirement at HS400 mode, force SDHCI + * interface clock to MMC_HS200_MAX_DTR (200 MHz) so that host + * controller CAR clock and the interface clock are rate matched. + */ + tegra_sdhci_set_clock(host, MMC_HS200_MAX_DTR); + } static void tegra_sdhci_reset(struct sdhci_host *host, u8 mask)