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vger.kernel.org; dmarc=none action=none header.from=nxp.com; Received: from AM6PR04MB4966.eurprd04.prod.outlook.com (2603:10a6:20b:2::14) by AM6PR04MB5206.eurprd04.prod.outlook.com (2603:10a6:20b:12::28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3611.22; Thu, 26 Nov 2020 11:16:47 +0000 Received: from AM6PR04MB4966.eurprd04.prod.outlook.com ([fe80::3cfc:a92e:75ad:ce4a]) by AM6PR04MB4966.eurprd04.prod.outlook.com ([fe80::3cfc:a92e:75ad:ce4a%3]) with mapi id 15.20.3611.025; Thu, 26 Nov 2020 11:16:47 +0000 From: Dong Aisheng To: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-mmc@vger.kernel.org, Dong Aisheng Subject: [PATCH RESEND v4 10/18] arm64: dts: imx8: switch to two cell scu clock binding Date: Thu, 26 Nov 2020 18:58:52 +0800 Message-Id: <20201126105900.26658-11-aisheng.dong@nxp.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20201126105900.26658-1-aisheng.dong@nxp.com> References: <20201126105900.26658-1-aisheng.dong@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: SG2PR03CA0160.apcprd03.prod.outlook.com (2603:1096:4:c9::15) To AM6PR04MB4966.eurprd04.prod.outlook.com (2603:10a6:20b:2::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from b29396-OptiPlex-7040.ap.freescale.net (119.31.174.66) by SG2PR03CA0160.apcprd03.prod.outlook.com (2603:1096:4:c9::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3632.7 via Frontend Transport; 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#clock-cells = <1>; - clocks = <&clk IMX_ADMA_UART0_CLK>, + clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; clock-indices = , ; clock-output-names = "uart0_lpcg_baud_clk", @@ -124,7 +124,7 @@ adma_subsys: bus@59000000 { uart1_lpcg: clock-controller@5a470000 { reg = <0x5a470000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_ADMA_UART1_CLK>, + clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; clock-indices = , ; clock-output-names = "uart1_lpcg_baud_clk", @@ -135,7 +135,7 @@ adma_subsys: bus@59000000 { uart2_lpcg: clock-controller@5a480000 { reg = <0x5a480000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_ADMA_UART2_CLK>, + clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; clock-indices = , ; clock-output-names = "uart2_lpcg_baud_clk", @@ -146,7 +146,7 @@ adma_subsys: bus@59000000 { uart3_lpcg: clock-controller@5a490000 { reg = <0x5a490000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_ADMA_UART3_CLK>, + clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; clock-indices = , ; clock-output-names = "uart3_lpcg_baud_clk", @@ -159,7 +159,7 @@ adma_subsys: bus@59000000 { interrupts = ; clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C0_CLK>; clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C0_CLK>; + assigned-clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; power-domains = <&pd IMX_SC_R_I2C_0>; status = "disabled"; @@ -170,7 +170,7 @@ adma_subsys: bus@59000000 { interrupts = ; clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C1_CLK>; clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C1_CLK>; + assigned-clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; power-domains = <&pd IMX_SC_R_I2C_1>; status = "disabled"; @@ -181,7 +181,7 @@ adma_subsys: bus@59000000 { interrupts = ; clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C2_CLK>; clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C2_CLK>; + assigned-clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; power-domains = <&pd IMX_SC_R_I2C_2>; status = "disabled"; @@ -192,7 +192,7 @@ adma_subsys: bus@59000000 { interrupts = ; clocks = <&adma_lpcg IMX_ADMA_LPCG_I2C3_CLK>; clock-names = "per"; - assigned-clocks = <&clk IMX_ADMA_I2C3_CLK>; + assigned-clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; power-domains = <&pd IMX_SC_R_I2C_3>; status = "disabled"; @@ -201,7 +201,7 @@ adma_subsys: bus@59000000 { i2c0_lpcg: clock-controller@5ac00000 { reg = <0x5ac00000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_ADMA_I2C0_CLK>, + clocks = <&clk IMX_SC_R_I2C_0 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; clock-indices = , ; clock-output-names = "i2c0_lpcg_clk", @@ -212,7 +212,7 @@ adma_subsys: bus@59000000 { i2c1_lpcg: clock-controller@5ac10000 { reg = <0x5ac10000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_ADMA_I2C1_CLK>, + clocks = <&clk IMX_SC_R_I2C_1 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; clock-indices = , ; clock-output-names = "i2c1_lpcg_clk", @@ -223,7 +223,7 @@ adma_subsys: bus@59000000 { i2c2_lpcg: clock-controller@5ac20000 { reg = <0x5ac20000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_ADMA_I2C2_CLK>, + clocks = <&clk IMX_SC_R_I2C_2 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; clock-indices = , ; clock-output-names = "i2c2_lpcg_clk", @@ -234,7 +234,7 @@ adma_subsys: bus@59000000 { i2c3_lpcg: clock-controller@5ac30000 { reg = <0x5ac30000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_ADMA_I2C3_CLK>, + clocks = <&clk IMX_SC_R_I2C_3 IMX_SC_PM_CLK_PER>, <&dma_ipg_clk>; clock-indices = , ; clock-output-names = "i2c3_lpcg_clk", diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index 4220a5cdc249..83945cc720e1 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -112,7 +112,7 @@ conn_subsys: bus@5b000000 { sdhc0_lpcg: clock-controller@5b200000 { reg = <0x5b200000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_CONN_SDHC0_CLK>, + clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>, <&conn_ipg_clk>, <&conn_axi_clk>; clock-indices = , , ; @@ -125,7 +125,7 @@ conn_subsys: bus@5b000000 { sdhc1_lpcg: clock-controller@5b210000 { reg = <0x5b210000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_CONN_SDHC1_CLK>, + clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>, <&conn_ipg_clk>, <&conn_axi_clk>; clock-indices = , , ; @@ -138,7 +138,7 @@ conn_subsys: bus@5b000000 { sdhc2_lpcg: clock-controller@5b220000 { reg = <0x5b220000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_CONN_SDHC2_CLK>, + clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>, <&conn_ipg_clk>, <&conn_axi_clk>; clock-indices = , , ; @@ -151,8 +151,8 @@ conn_subsys: bus@5b000000 { enet0_lpcg: clock-controller@5b230000 { reg = <0x5b230000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>, - <&clk IMX_CONN_ENET0_ROOT_CLK>, + clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; clock-indices = , , , , @@ -168,8 +168,8 @@ conn_subsys: bus@5b000000 { enet1_lpcg: clock-controller@5b240000 { reg = <0x5b240000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>, - <&clk IMX_CONN_ENET1_ROOT_CLK>, + clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>, <&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>; clock-indices = , , , , diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index babe6c3e2c76..813dbac71d10 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -157,9 +157,11 @@ lsio_subsys: bus@5d000000 { pwm0_lpcg: clock-controller@5d400000 { reg = <0x5d400000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM0_CLK>, <&clk IMX_LSIO_PWM0_CLK>, - <&clk IMX_LSIO_PWM0_CLK>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM0_CLK>; + clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; clock-indices = , , , , ; @@ -174,9 +176,11 @@ lsio_subsys: bus@5d000000 { pwm1_lpcg: clock-controller@5d410000 { reg = <0x5d410000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM1_CLK>, <&clk IMX_LSIO_PWM1_CLK>, - <&clk IMX_LSIO_PWM1_CLK>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM1_CLK>; + clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; clock-indices = , , , , ; @@ -191,9 +195,11 @@ lsio_subsys: bus@5d000000 { pwm2_lpcg: clock-controller@5d420000 { reg = <0x5d420000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM2_CLK>, <&clk IMX_LSIO_PWM2_CLK>, - <&clk IMX_LSIO_PWM2_CLK>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM2_CLK>; + clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; clock-indices = , , , , ; @@ -208,9 +214,11 @@ lsio_subsys: bus@5d000000 { pwm3_lpcg: clock-controller@5d430000 { reg = <0x5d430000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM3_CLK>, <&clk IMX_LSIO_PWM3_CLK>, - <&clk IMX_LSIO_PWM3_CLK>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM3_CLK>; + clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; clock-indices = , , , , ; @@ -225,9 +233,11 @@ lsio_subsys: bus@5d000000 { pwm4_lpcg: clock-controller@5d440000 { reg = <0x5d440000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM4_CLK>, <&clk IMX_LSIO_PWM4_CLK>, - <&clk IMX_LSIO_PWM4_CLK>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM4_CLK>; + clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>; clock-indices = , , , , ; @@ -242,9 +252,11 @@ lsio_subsys: bus@5d000000 { pwm5_lpcg: clock-controller@5d450000 { reg = <0x5d450000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM5_CLK>, <&clk IMX_LSIO_PWM5_CLK>, - <&clk IMX_LSIO_PWM5_CLK>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM5_CLK>; + clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>; clock-indices = , , , , ; @@ -259,9 +271,11 @@ lsio_subsys: bus@5d000000 { pwm6_lpcg: clock-controller@5d460000 { reg = <0x5d460000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM6_CLK>, <&clk IMX_LSIO_PWM6_CLK>, - <&clk IMX_LSIO_PWM6_CLK>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM6_CLK>; + clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>; clock-indices = , , , , ; @@ -276,9 +290,11 @@ lsio_subsys: bus@5d000000 { pwm7_lpcg: clock-controller@5d470000 { reg = <0x5d470000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM7_CLK>, <&clk IMX_LSIO_PWM7_CLK>, - <&clk IMX_LSIO_PWM7_CLK>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM7_CLK>; + clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, + <&lsio_bus_clk>, + <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>; clock-indices = , , , , ; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts index a3f8cf195974..b5352706e3f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ai_ml.dts @@ -133,7 +133,7 @@ &usdhc1 { #address-cells = <1>; #size-cells = <0>; - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; + assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -151,7 +151,7 @@ /* SD */ &usdhc2 { - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; + assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 46437d3c7a04..c40bbb313b78 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -173,7 +173,7 @@ }; &usdhc1 { - assigned-clocks = <&clk IMX_CONN_SDHC0_CLK>; + assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -185,7 +185,7 @@ }; &usdhc2 { - assigned-clocks = <&clk IMX_CONN_SDHC1_CLK>; + assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <200000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index cd7a482dc3ff..095d3f69a9b7 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -58,7 +58,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; @@ -69,7 +69,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; @@ -80,7 +80,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; @@ -91,7 +91,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&A35_L2>; - clocks = <&clk IMX_A35_CLK>; + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; operating-points-v2 = <&a35_opp_table>; #cooling-cells = <2>; }; @@ -165,7 +165,7 @@ clk: clock-controller { compatible = "fsl,imx8qxp-clk"; - #clock-cells = <1>; + #clock-cells = <2>; clocks = <&xtal32k &xtal24m>; clock-names = "xtal_32KHz", "xtal_24Mhz"; };