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[120.74.102.185]) by smtp.gmail.com with ESMTPSA id m13sm3703040pjr.30.2020.11.05.18.28.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Nov 2020 18:28:51 -0800 (PST) From: AKASHI Takahiro To: ulf.hansson@linaro.org, adrian.hunter@intel.com Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, ben.chuang@genesyslogic.com.tw, greg.tu@genesyslogic.com.tw, AKASHI Takahiro Subject: [RFC PATCH v3.1 18/27] mmc: sdhci-uhs2: add clock operations Date: Fri, 6 Nov 2020 11:27:17 +0900 Message-Id: <20201106022726.19831-19-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201106022726.19831-1-takahiro.akashi@linaro.org> References: <20201106022726.19831-1-takahiro.akashi@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org This is a sdhci version of mmc's uhs2_[enable|disable]_clk operations. Signed-off-by: Ben Chuang Signed-off-by: AKASHI Takahiro --- drivers/mmc/host/sdhci-uhs2.c | 41 +++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) -- 2.28.0 diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c index 994dff967e85..55362ace1857 100644 --- a/drivers/mmc/host/sdhci-uhs2.c +++ b/drivers/mmc/host/sdhci-uhs2.c @@ -11,6 +11,7 @@ */ #include +#include #include #include "sdhci.h" @@ -385,6 +386,42 @@ void sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) __sdhci_uhs2_set_ios(mmc, ios); } +static void sdhci_uhs2_disable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); +} + +static void sdhci_uhs2_enable_clk(struct mmc_host *mmc) +{ + struct sdhci_host *host = mmc_priv(mmc); + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + ktime_t timeout; + + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 20 ms */ + timeout = ktime_add_ms(ktime_get(), 20); + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_INT_STABLE) + break; + if (timedout) { + pr_err("%s: Internal clock never stabilised.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return; + } + udelay(10); + } +} + /*****************************************************************************\ * * * Driver init/exit * @@ -556,6 +593,10 @@ static int sdhci_uhs2_host_ops_init(struct sdhci_host *host) if (!host->mmc_host_ops.uhs2_detect_init) host->mmc_host_ops.uhs2_detect_init = sdhci_uhs2_do_detect_init; + if (!host->mmc_host_ops.uhs2_disable_clk) + host->mmc_host_ops.uhs2_disable_clk = sdhci_uhs2_disable_clk; + if (!host->mmc_host_ops.uhs2_enable_clk) + host->mmc_host_ops.uhs2_enable_clk = sdhci_uhs2_enable_clk; return 0; }