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[66.175.222.153]) by smtp.gmail.com with ESMTPSA id f30sm33985090pga.20.2019.12.02.06.41.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Dec 2019 06:41:26 -0800 (PST) From: Jun Nie To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, adrian.hunter@intel.com, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH 2/4] mmc: sdhci: dt: Add DMA boundary and HS400 properties Date: Mon, 2 Dec 2019 22:41:02 +0800 Message-Id: <20191202144104.5069-3-jun.nie@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202144104.5069-1-jun.nie@linaro.org> References: <20191202144104.5069-1-jun.nie@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org DMA memory cannot cross specific boundary on some controller, such as 128MB on SDHCI Designware. Add sdhci-dma-mem-boundary property to split DMA operation in such case. sdhci-ctrl-hs400 specify the HS400 mode setting for register SDHCI_HOST_CONTROL2(offset 0x3E:bit[2:0]). Because this value is not defined in SDHC Standard specification. Signed-off-by: Jun Nie --- Documentation/devicetree/bindings/mmc/sdhci.txt | 8 ++++++++ 1 file changed, 8 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/mmc/sdhci.txt b/Documentation/devicetree/bindings/mmc/sdhci.txt index 0e9923a64024..e6d7feb9a741 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci.txt @@ -11,3 +11,11 @@ Optional properties: - sdhci-caps: The sdhci capabilities register is incorrect. This 64bit property corresponds to the bits in the sdhci capability register. If the bit is on in the property then the bit should be turned on. +- sdhci-dma-mem-boundary: The sdhci controller DMA memory space boundary. + If the controller's DMA cannot cross a specific memory space boundary, + such as 128MB, set this value in dt and driver will split the DMA + operation when crossing such boundary. +- sdhci-ctrl-hs400: The HS400 is not defined in SDHC Standard specification + for SDHCI_HOST_CONTROL2(offset 0x3E:bit[2:0]). Different controllers have + have different value for HS400 mode. If 0x5 is not the HS400 mode value + for your controller, you should specify the value with this property.