From patchwork Mon Feb 5 12:50:15 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 126849 Delivered-To: patch@linaro.org Received: by 10.46.124.24 with SMTP id x24csp1942093ljc; Mon, 5 Feb 2018 04:51:44 -0800 (PST) X-Google-Smtp-Source: AH8x226tKwVR50oseKXjb6RXla0+npVdLb8Y2ZSnrAHhkW5sApwy6nmWnzaPYna8K8+XbKQcugi5 X-Received: by 10.101.87.132 with SMTP id b4mr38102353pgr.332.1517835104421; Mon, 05 Feb 2018 04:51:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1517835104; cv=none; d=google.com; s=arc-20160816; b=Q7LpzXR9imoAqnn8AUKEF37srlGSRhCHFV1tM1t8fqYdA6QOCMDZQEuZYzMyDcNqHm jQ3PTF9Nd6RLfEQKWbULIrasdoqNN4COA1Bco1tO6dgouPjxVoNJ8UjlK2y7iWih0r2Y DoEkir53CaLbYrTvVDafjNkeIrXcpKcWSXm0cuN0T4rc9emMiK0HmN3x6KK8EeAK8wR0 aShPZUC6hJiXmIMP9w6Hsb0ZnLA/kIIoBvxeW6nluNgByYOKKDYV4QwI2mHnhLCfI1rb gLfsNEvBP0fA4NcKCLwENy3AhEzxm7kDCsYd+v8diatXkv+/5OxkIj14Fxaol7n+tgVu ikag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature:arc-authentication-results; bh=43+C8fUYxsWpDsW2PmYCXjqc6+nA+LsBPy1Xx5dN0uk=; b=0NsXxln29dCFLwQfdF0OuPgdhQEqVJ9bgwIJX5Y+fuvo9fNHTSLZTnfBfNaeuIB0mq hMgy17SQYfV/vnWCjZQazvWm/YDQpGNOmYja0We+wz23lgOIkryFL4cGKfHYyPgd6iBa 3JRlhHKorckaGviAIrY+kKJhaemD6LJoJzbA0fg9pUhG88Y4QKCAqXq9dqiOZRNF3jWd 8FSMxOegDhy4yasg1vNAbWwQB+FbKbKSLPX05ouSTWFbauyorcDrTL7clA9ITUVghR8D RzzZk8O8t3Nf3rbvwdSQCI9MPvR+2vNyeZ1jNmhU7BfkcaBqAqmMW+hWcAt8+CjMLHuN 6JdA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=Grz4b8Mz; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id q23si727871pff.403.2018.02.05.04.51.44; Mon, 05 Feb 2018 04:51:44 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.s=ti-com-17Q1 header.b=Grz4b8Mz; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=fail (p=QUARANTINE sp=NONE dis=QUARANTINE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753069AbeBEMvl (ORCPT + 6 others); Mon, 5 Feb 2018 07:51:41 -0500 Received: from lelnx193.ext.ti.com ([198.47.27.77]:63857 "EHLO lelnx193.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752986AbeBEMv3 (ORCPT ); Mon, 5 Feb 2018 07:51:29 -0500 Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id w15Comua011236; Mon, 5 Feb 2018 06:50:48 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1517835048; bh=dSvUAyWQITYffHWTaBPkMuwbxExOhl29rE6BsCK5oFw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Grz4b8Mz6v4vxlLgY+ANaSfjsupYC6ykNTqLeNhvEMrk3C9ZYR4iA4o3AaDENftMk DuPgbj+gbJ6QES3dQNVr+V4t4bSYuNh1sq+B9ALkMaSjddijX60u1ueS//P+oEeS8J bteOo7n+RB0Nf12vG+DTu8IOuwqVveiZYwZH6NmE= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15Com90019683; Mon, 5 Feb 2018 06:50:48 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1261.35; Mon, 5 Feb 2018 06:50:47 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1261.35 via Frontend Transport; Mon, 5 Feb 2018 06:50:47 -0600 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w15CoaGX023963; Mon, 5 Feb 2018 06:50:44 -0600 From: Kishon Vijay Abraham I To: Ulf Hansson , Tony Lindgren , Adrian Hunter CC: Rob Herring , Mark Rutland , Russell King , Kishon Vijay Abraham I , , , , , Subject: [PATCH v2 02/16] mmc: sdhci-omap: Add card_busy host ops Date: Mon, 5 Feb 2018 18:20:15 +0530 Message-ID: <20180205125029.21570-3-kishon@ti.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180205125029.21570-1-kishon@ti.com> References: <20180205125029.21570-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add card_busy host ops in sdhci_omap to check card busy status. The voltage switching sequence for AM572x platform is mentioned in Figure 25-48. eMMC/SD/SDIO Power Switching Procedure of AM572x Sitara Processors Silicon Revision 2.0, 1.1 TRM (SPRUHZ6I - October 2014–Revised April 2017 [1]). In the voltage switching sequence, CLKEXTFREE bit in MMCHS_CON should also be set after switching to 1.8v which is also taken care in the card_busy ops. [1] -> http://www.ti.com/lit/ug/spruhz6i/spruhz6i.pdf Signed-off-by: Kishon Vijay Abraham I --- drivers/mmc/host/sdhci-omap.c | 52 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) -- 2.11.0 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c index 96985786cadf..df927f3faaf6 100644 --- a/drivers/mmc/host/sdhci-omap.c +++ b/drivers/mmc/host/sdhci-omap.c @@ -31,11 +31,17 @@ #define SDHCI_OMAP_CON 0x12c #define CON_DW8 BIT(5) #define CON_DMA_MASTER BIT(20) +#define CON_CLKEXTFREE BIT(16) +#define CON_PADEN BIT(15) #define CON_INIT BIT(1) #define CON_OD BIT(0) #define SDHCI_OMAP_CMD 0x20c +#define SDHCI_OMAP_PSTATE 0x0224 +#define PSTATE_DLEV_DAT0 BIT(20) +#define PSTATE_DATI BIT(1) + #define SDHCI_OMAP_HCTL 0x228 #define HCTL_SDBP BIT(8) #define HCTL_SDVS_SHIFT 9 @@ -191,6 +197,51 @@ static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host, } } +static int sdhci_omap_card_busy(struct mmc_host *mmc) +{ + u32 reg, ac12; + int ret = false; + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host; + struct sdhci_omap_host *omap_host; + u32 ier = host->ier; + + pltfm_host = sdhci_priv(host); + omap_host = sdhci_pltfm_priv(pltfm_host); + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); + ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12); + reg &= ~CON_CLKEXTFREE; + if (ac12 & AC12_V1V8_SIGEN) + reg |= CON_CLKEXTFREE; + reg |= CON_PADEN; + sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); + + disable_irq(host->irq); + ier |= SDHCI_INT_CARD_INT; + sdhci_writel(host, ier, SDHCI_INT_ENABLE); + sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE); + + /* + * Delay is required for PSTATE to correctly reflect + * DLEV/CLEV values after PADEN is set. + */ + usleep_range(50, 100); + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE); + if ((reg & PSTATE_DATI) || !(reg & PSTATE_DLEV_DAT0)) + ret = true; + + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON); + reg &= ~(CON_CLKEXTFREE | CON_PADEN); + sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg); + + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); + enable_irq(host->irq); + + return ret; +} + static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios) { @@ -562,6 +613,7 @@ static int sdhci_omap_probe(struct platform_device *pdev) host->mmc_host_ops.start_signal_voltage_switch = sdhci_omap_start_signal_voltage_switch; host->mmc_host_ops.set_ios = sdhci_omap_set_ios; + host->mmc_host_ops.card_busy = sdhci_omap_card_busy; sdhci_read_caps(host); host->caps |= SDHCI_CAN_DO_ADMA2;