From patchwork Wed Nov 16 10:51:18 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ulf Hansson X-Patchwork-Id: 82474 Delivered-To: patches@linaro.org Received: by 10.140.97.165 with SMTP id m34csp82410qge; Wed, 16 Nov 2016 02:51:42 -0800 (PST) X-Received: by 10.194.133.233 with SMTP id pf9mr1659315wjb.15.1479293502416; Wed, 16 Nov 2016 02:51:42 -0800 (PST) Return-Path: Received: from mail-wm0-x235.google.com (mail-wm0-x235.google.com. [2a00:1450:400c:c09::235]) by mx.google.com with ESMTPS id f125si6752768wmf.44.2016.11.16.02.51.42 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 16 Nov 2016 02:51:42 -0800 (PST) Received-SPF: pass (google.com: domain of ulf.hansson@linaro.org designates 2a00:1450:400c:c09::235 as permitted sender) client-ip=2a00:1450:400c:c09::235; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org; spf=pass (google.com: domain of ulf.hansson@linaro.org designates 2a00:1450:400c:c09::235 as permitted sender) smtp.mailfrom=ulf.hansson@linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by mail-wm0-x235.google.com with SMTP id t79so63892693wmt.0 for ; Wed, 16 Nov 2016 02:51:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2nsnSX0fVfqkd1RgLh6oWN0LZeVX087MUuLqhBMve6Y=; b=cFslZtj+9H+jr0vzhJGwtQjGM+IcwGX6Yc4DV3anyw5uAdEnMLAfycEohzGEddUEGJ GqdMv3OJM5hCoc9OCBf0KJenMKVqy2nMa+k21gIAG5CRp55m8Hq549fc1ilyDKTQw3TR Fh9YZKLbirj6L1rkssc5nFbhM91pvVdjTi/2A= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2nsnSX0fVfqkd1RgLh6oWN0LZeVX087MUuLqhBMve6Y=; b=g2AcfIKot4JN4kLMsFdiJloTb/vImcKYVJO7HXjNwfYG6VAIwHQQr+GtUk6DBTkJZj KlKxUihYvga0hKF2BLyQyV8Xilo4VNTTa95T3CSeIhD3xZH3z0LbTUlqjvulm2yM+cEX HlSIwCawlDRmDKYwrqAAsyV/m6Yrgie6t1VAX2XediCfQ102g+8dARCiS8CS0+EmfFOo fdsPRC4anaBDJIQMAAa0XNkaxzQvaDEHMyfWCLxd7TpDxePbyo1LtKzvNQhtf1YHjN+7 4x0awhsnaOCe2Te3eoOojQmo9n8i+oi8D/EMG7frNSwUAWQ8t2xD7Mbn2q7xTzPPulJz wNww== X-Gm-Message-State: ABUngvfyAfjbclHcC6NG4vbX2keDXCJsvX90OJ7dW5jH9vHMmw4tmdwnvuUDO5ceuye6nJ7m7lM= X-Received: by 10.25.221.208 with SMTP id w77mr826423lfi.39.1479293501996; Wed, 16 Nov 2016 02:51:41 -0800 (PST) Return-Path: Received: from uffe-Latitude-E6430s.ideon.se ([85.235.10.227]) by smtp.gmail.com with ESMTPSA id 34sm7711369lja.25.2016.11.16.02.51.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 16 Nov 2016 02:51:40 -0800 (PST) From: Ulf Hansson To: linux-mmc@vger.kernel.org, Ulf Hansson Cc: Jaehoon Chung , Adrian Hunter , Linus Walleij , Chaotian Jing , Stephen Boyd , Michael Walle , Yong Mao , Shawn Lin Subject: [PATCH 6/9] mmc: core: Update CMD13 polling policy when switch to HS DDR mode Date: Wed, 16 Nov 2016 11:51:18 +0100 Message-Id: <1479293481-20186-7-git-send-email-ulf.hansson@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479293481-20186-1-git-send-email-ulf.hansson@linaro.org> References: <1479293481-20186-1-git-send-email-ulf.hansson@linaro.org> According to the JEDEC specification, during bus timing change operations for mmc, sending a CMD13 could trigger CRC errors. As switching to HS DDR mode indeed causes a bus timing change, polling with CMD13 to detect card busy, may thus potentially trigger CRC errors. Currently these errors are treated as the switch to HS DDR mode failed. To improve this behaviour, let's instead tell __mmc_switch() to retry when it encounters CRC errors during polling. Moreover, when switching to HS DDR mode, let's make sure the CMD13 polling is done by having the mmc host and the mmc card, being configured to operate at the same selected bus speed timing. Fix this by providing MMC_TIMING_MMC_DDR52 as the timing parameter to __mmc_switch(). Signed-off-by: Ulf Hansson --- drivers/mmc/core/mmc.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) -- 1.9.1 diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 15dd51c..3268fcd 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -1040,10 +1040,12 @@ static int mmc_select_hs_ddr(struct mmc_card *card) ext_csd_bits = (bus_width == MMC_BUS_WIDTH_8) ? EXT_CSD_DDR_BUS_WIDTH_8 : EXT_CSD_DDR_BUS_WIDTH_4; - err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, - EXT_CSD_BUS_WIDTH, - ext_csd_bits, - card->ext_csd.generic_cmd6_time); + err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, + EXT_CSD_BUS_WIDTH, + ext_csd_bits, + card->ext_csd.generic_cmd6_time, + MMC_TIMING_MMC_DDR52, + true, true, true); if (err) { pr_err("%s: switch to bus width %d ddr failed\n", mmc_hostname(host), 1 << bus_width); @@ -1086,9 +1088,6 @@ static int mmc_select_hs_ddr(struct mmc_card *card) if (err) err = __mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330); - if (!err) - mmc_set_timing(host, MMC_TIMING_MMC_DDR52); - return err; }