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[209.132.180.67]) by mx.google.com with ESMTP id xs9si8030476pab.86.2016.11.03.06.32.14; Thu, 03 Nov 2016 06:32:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of linux-mmc-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-mmc-owner@vger.kernel.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754146AbcKCNcN (ORCPT + 3 others); Thu, 3 Nov 2016 09:32:13 -0400 Received: from mail-pf0-f176.google.com ([209.85.192.176]:34855 "EHLO mail-pf0-f176.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753153AbcKCNcN (ORCPT ); Thu, 3 Nov 2016 09:32:13 -0400 Received: by mail-pf0-f176.google.com with SMTP id i88so31895399pfk.2 for ; Thu, 03 Nov 2016 06:32:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ce2ouCt8ZNihef4jqkDW9fHRlhAm+ZgaS+YWTr4zOH4=; b=hIQrsc8pTo9X5RV1F+pUsi2EyyyESRJ+3E55hplBvwas+DpCn790PL6t6gkoqH6P9X 33DVZFAmo/5hEaOR3eNw4jqfn7KqsdEHvq16C5S2XxaLVmllVbvsAFEc6Kz4UmM54zHg Qr0gcorM7L83jNyGU51GkxdPTc5Brx6dQAX1o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ce2ouCt8ZNihef4jqkDW9fHRlhAm+ZgaS+YWTr4zOH4=; b=DgeqD1g16LLogwOHrryTtrSCQu+BQRXOQhzak8GcL4Wjqpi43wwSewBA7wmljda2qQ GG79j18UibRwfyMjA+SQpzZCxw/KYzRSCrubFiaIf/s81LrZCNCNqcNP/6vLh3ZktD/T pdDD8GJf21sTktm7XgcBjCBqlPbzLXYwq/OUx/Qm3gQcA2gC3r0XBla3mzdkS5EtrbLt R4NhjZNhm8Km2Mw/7L/WBe/++pZZLqtdS2fARwVpcZp8GkAMKXIEE+KGysSvh4E7Tajs 8uePBPWaSBVjZFw0O1GHct75gCJnnQB3F6ElVwiRiEhn0/3pdPvVtATBFlWDZOr9e6ds rKDA== X-Gm-Message-State: ABUngvfpVvZAWaE4rFNPdMIzAxin3vVG7Dx11lOhtBNSnBAeBW1D50ErQNtWkJsO32JjXAuV X-Received: by 10.98.17.80 with SMTP id z77mr16900449pfi.166.1478179932320; Thu, 03 Nov 2016 06:32:12 -0700 (PDT) Received: from localhost.localdomain ([188.42.252.253]) by smtp.gmail.com with ESMTPSA id j192sm12926803pfc.60.2016.11.03.06.32.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 03 Nov 2016 06:32:11 -0700 (PDT) From: Jun Nie To: shawn.guo@linaro.org, xie.baoyou@zte.com.cn Cc: ulf.hansson@linaro.org, jh80.chung@samsung.com, jason.liu@linaro.org, linux-mmc@vger.kernel.org, Jun Nie Subject: [PATCH v3 3/5] Documentation: synopsys-dw-mshc: add binding for fifo quirks Date: Thu, 3 Nov 2016 21:31:39 +0800 Message-Id: <1478179901-25645-4-git-send-email-jun.nie@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1478179901-25645-1-git-send-email-jun.nie@linaro.org> References: <1478179901-25645-1-git-send-email-jun.nie@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Add fifo-addr property and fifo-watermark-quirk property to synopsys-dw-mshc bindings. It is intended to provide more dt interface to support SoCs specific configuration. Signed-off-by: Jun Nie --- Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-mmc" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt index 4e00e85..8bf2e41 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt @@ -76,6 +76,17 @@ Optional properties: * broken-cd: as documented in mmc core bindings. +* data-addr: Override fifo address with value provided by DT. The default FIFO reg + offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A) by + driver. If the controller does not follow this rule, please use this property + to set fifo address in device tree. + +* fifo-watermark-aligned: Data done irq is expected if data length is less than + watermark in PIO mode. But fifo watermark is requested to be aligned with data + length in some SoC so that TX/RX irq can be generated with data done irq. Add this + watermark quirk to mark this requirement and force fifo watermark setting + accordingly. + * vmmc-supply: The phandle to the regulator to use for vmmc. If this is specified we'll defer probe until we can find this regulator. @@ -103,6 +114,8 @@ board specific portions as listed below. interrupts = <0 75 0>; #address-cells = <1>; #size-cells = <0>; + data-addr = <0x200>; + fifo-watermark-aligned; }; [board specific internal DMA resources]