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[209.132.180.67]) by mx.google.com with ESMTP id vy5si10600385pac.2.2015.09.07.04.21.29; Mon, 07 Sep 2015 04:21:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751564AbbIGLVS (ORCPT + 28 others); Mon, 7 Sep 2015 07:21:18 -0400 Received: from mail-pa0-f49.google.com ([209.85.220.49]:32968 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751451AbbIGLVM (ORCPT ); Mon, 7 Sep 2015 07:21:12 -0400 Received: by pacex6 with SMTP id ex6so94898067pac.0 for ; Mon, 07 Sep 2015 04:21:12 -0700 (PDT) X-Received: by 10.66.159.197 with SMTP id xe5mr45239262pab.32.1441624871904; Mon, 07 Sep 2015 04:21:11 -0700 (PDT) Received: from localhost.localdomain ([202.62.93.139]) by smtp.gmail.com with ESMTPSA id fm5sm11654737pbb.60.2015.09.07.04.21.08 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 07 Sep 2015 04:21:10 -0700 (PDT) From: Vaibhav Hiremath To: linux-mmc@vger.kernel.org Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, robh+dt@kernel.org, ulf.hansson@linaro.org, Vaibhav Hiremath Subject: [PATCH-v2 3/7] mmc: sdhci-pxav3: Add platform specific set_clock ops Date: Mon, 7 Sep 2015 16:48:37 +0530 Message-Id: <1441624721-15612-4-git-send-email-vaibhav.hiremath@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1441624721-15612-1-git-send-email-vaibhav.hiremath@linaro.org> References: <1441624721-15612-1-git-send-email-vaibhav.hiremath@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: vaibhav.hiremath@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.178 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , In case of PXA1928 & family of devices, the TX BUS and internal clock need to be set as part of ->set_clock() ops, so this patch adds platform specific ->set_clock() operation. Note that, in order to not break other platforms, this patch introduced the flag, which controls whether controller/platform specific clock configuration needs to be executed. Signed-off-by: Vaibhav Hiremath --- drivers/mmc/host/sdhci-pxav3.c | 46 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-pxav3.c index aecae04..c2b2b78 100644 --- a/drivers/mmc/host/sdhci-pxav3.c +++ b/drivers/mmc/host/sdhci-pxav3.c @@ -48,6 +48,10 @@ #define SDCFG_GEN_PAD_CLK_CNT_MASK 0xFF #define SDCFG_GEN_PAD_CLK_CNT_SHIFT 24 +#define SD_FIFO_PARAM 0x104 +#define INTERNAL_CLK_GATE_CTRL BIT(8) +#define INTERNAL_CLK_GATE_ON BIT(9) + #define SD_SPI_MODE 0x108 #define SD_CE_ATA_1 0x10C @@ -57,6 +61,9 @@ #define SD_RX_CFG_REG 0x114 +#define TX_CFG_REG 0x118 +#define TX_INTERNAL_SEL_BUS_CLK BIT(30) + /* IO Power control */ #define IO_PWR_AKEY_ASFAR 0xbaba #define IO_PWR_AKEY_ASSAR 0xeb10 @@ -68,6 +75,9 @@ struct sdhci_pxa_data { u8 sdclk_delay_shift; u8 sdclk_sel_mask; u8 sdclk_sel_shift; + + /* set this if platform needs separate clock configuration */ + bool set_pltfrm_clk; /* * We have few more differences, add them along with their * respective feature support @@ -90,6 +100,7 @@ static struct sdhci_pxa_data pxav3_data_v1 = { .sdclk_delay_shift = 9, .sdclk_sel_mask = 0x1, .sdclk_sel_shift = 8, + .set_pltfrm_clk = false, }; static struct sdhci_pxa_data pxav3_data_v2 = { @@ -99,6 +110,7 @@ static struct sdhci_pxa_data pxav3_data_v2 = { /* Only set SDCLK_SEL1, as driver uses default value of SDCLK_SEL0 */ .sdclk_sel_mask = 0x3, .sdclk_sel_shift = 2, /* SDCLK_SEL1 */ + .set_pltfrm_clk = true, }; /* @@ -375,8 +387,40 @@ static void pxav3_voltage_switch(struct sdhci_host *host, writel(val, pxa->io_pwr_reg); } +static void pxav3_set_tx_clock(struct sdhci_host *host) +{ + u32 val; + + val = sdhci_readl(host, TX_CFG_REG); + val |= TX_INTERNAL_SEL_BUS_CLK; + sdhci_writel(host, val, TX_CFG_REG); +} + +static void pxav3_set_clock(struct sdhci_host *host, unsigned int clock) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_pxa *pxa = pltfm_host->priv; + + /* We still use common sdhci_set_clock() */ + sdhci_set_clock(host, clock); + + /* platform/controller specific clock configuration */ + if (pxa->data->set_pltfrm_clk && clock != 0) { + u32 val; + + val = sdhci_readw(host, SD_FIFO_PARAM); + /* Internal clock gate ON and CTRL = 0b11 */ + val |= INTERNAL_CLK_GATE_CTRL | INTERNAL_CLK_GATE_ON; + sdhci_writew(host, val, SD_FIFO_PARAM); + + /* TX internal clock selection */ + pxav3_set_tx_clock(host); + } + +} + static const struct sdhci_ops pxav3_sdhci_ops = { - .set_clock = sdhci_set_clock, + .set_clock = pxav3_set_clock, .platform_send_init_74_clocks = pxav3_gen_init_74_clocks, .get_max_clock = sdhci_pltfm_clk_get_max_clock, .set_bus_width = sdhci_set_bus_width,