From patchwork Wed May 28 13:46:38 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 31064 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ie0-f197.google.com (mail-ie0-f197.google.com [209.85.223.197]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id E677A20068 for ; Wed, 28 May 2014 13:46:53 +0000 (UTC) Received: by mail-ie0-f197.google.com with SMTP id rd18sf56539773iec.8 for ; Wed, 28 May 2014 06:46:53 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=oBaVh2o5meFNdpCSdH50/1elrZyLQeP+BNU66k3wSSg=; b=mXTxeLNFw4XM/XYO2b8ovYFQSDG9iWzI6yHI3YSAXx1EzEic1rlJVH/G/YRVhKo0Na SkhLaxFpkvEl5RFsR51tKa2YYUGb0fnvQcmBYJySZoPRMQJTvaHoKuXCB3kv6ryoktgs BlOOwVAN9ayybPsh6T54V7q8enZA9uJuG1X1XonmH4TduzORnoDSQRpyiDNjlNv4OeA9 xUciZli6fsaXyHkdL4TLdMLXbKtIPvUTjapAj76nV3s7ICxtPAS/ws9CDeWKUgW2gTMD Xq0QkqwdxbqSwk7dHEgoP0FkgihZVvQUR1REdjxnqbNgx/EcxMJmaCXepdMkHRpJuFia cz9g== X-Gm-Message-State: ALoCoQmF87Lec76C/qDKULLsSg9wm6M9MtuB9eTKZnyqEjsFxIDWbxYisSJ0bfPy4JaED5elu8/c X-Received: by 10.182.105.41 with SMTP id gj9mr16641223obb.30.1401284813369; Wed, 28 May 2014 06:46:53 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.84.239 with SMTP id l102ls85455qgd.81.gmail; Wed, 28 May 2014 06:46:53 -0700 (PDT) X-Received: by 10.52.4.40 with SMTP id h8mr844713vdh.95.1401284813209; Wed, 28 May 2014 06:46:53 -0700 (PDT) Received: from mail-ve0-f174.google.com (mail-ve0-f174.google.com [209.85.128.174]) by mx.google.com with ESMTPS id rn19si10553856vdb.22.2014.05.28.06.46.53 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 28 May 2014 06:46:53 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.174 as permitted sender) client-ip=209.85.128.174; Received: by mail-ve0-f174.google.com with SMTP id jw12so12557755veb.33 for ; Wed, 28 May 2014 06:46:53 -0700 (PDT) X-Received: by 10.52.227.138 with SMTP id sa10mr28908846vdc.25.1401284813041; Wed, 28 May 2014 06:46:53 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp204332vcb; Wed, 28 May 2014 06:46:52 -0700 (PDT) X-Received: by 10.66.192.73 with SMTP id he9mr46753924pac.88.1401284812194; Wed, 28 May 2014 06:46:52 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id th10si23912978pab.18.2014.05.28.06.46.51; Wed, 28 May 2014 06:46:51 -0700 (PDT) Received-SPF: none (google.com: linux-mmc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753974AbaE1Nqp (ORCPT + 6 others); Wed, 28 May 2014 09:46:45 -0400 Received: from mail-wg0-f41.google.com ([74.125.82.41]:34674 "EHLO mail-wg0-f41.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752968AbaE1Nqn (ORCPT ); Wed, 28 May 2014 09:46:43 -0400 Received: by mail-wg0-f41.google.com with SMTP id z12so10981062wgg.0 for ; Wed, 28 May 2014 06:46:42 -0700 (PDT) X-Received: by 10.180.100.41 with SMTP id ev9mr49572272wib.22.1401284802262; Wed, 28 May 2014 06:46:42 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-78-149-4-211.as13285.net. [78.149.4.211]) by mx.google.com with ESMTPSA id rw4sm43395149wjb.44.2014.05.28.06.46.40 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 28 May 2014 06:46:41 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Russell King , Ulf Hansson , linux-mmc@vger.kernel.org Cc: Chris Ball , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linus.walleij@linaro.org, Srinivas Kandagatla Subject: [PATCH v4 05/13] mmc: mmci: Add Qcom datactrl register variant Date: Wed, 28 May 2014 14:46:38 +0100 Message-Id: <1401284798-16645-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1401284608-16428-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1401284608-16428-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: srinivas.kandagatla@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.174 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Srinivas Kandagatla Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl register. Bit position datactrl[16:4] hold the true block size instead of power of 2. Signed-off-by: Srinivas Kandagatla Reviewed-by: Linus Walleij --- drivers/mmc/host/mmci.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index aa2d381..23401b0 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -60,6 +60,8 @@ static unsigned int fmax = 515633; * @sdio: variant supports SDIO * @st_clkdiv: true if using a ST-specific clock divider algorithm * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register + * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl + * register * @pwrreg_powerup: power up value for MMCIPOWER register * @signal_direction: input/out direction of bus signals can be indicated * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock @@ -75,6 +77,7 @@ struct variant_data { bool sdio; bool st_clkdiv; bool blksz_datactrl16; + bool blksz_datactrl4; u32 pwrreg_powerup; bool signal_direction; bool pwrreg_clkgate; @@ -164,6 +167,7 @@ static struct variant_data variant_qcom = { .fifosize = 16 * 4, .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, + .blksz_datactrl4 = true, .datalength_bits = 24, .pwrreg_powerup = MCI_PWR_UP, }; @@ -739,6 +743,8 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) if (variant->blksz_datactrl16) datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); + else if (variant->blksz_datactrl4) + datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); else datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;