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[78.149.4.211]) by mx.google.com with ESMTPSA id ed6sm2791420wib.20.2014.05.23.05.51.46 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 23 May 2014 05:51:47 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Russell King , Ulf Hansson , linux-mmc@vger.kernel.org Cc: Chris Ball , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linus.walleij@linaro.org, Srinivas Kandagatla Subject: [PATCH v3 06/13] mmc: mmci: Qcomm: Add 3 clock cycle delay after register write Date: Fri, 23 May 2014 13:51:44 +0100 Message-Id: <1400849504-7302-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1400849362-7007-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1400849362-7007-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: srinivas.kandagatla@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.173 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Srinivas Kandagatla Most of the Qcomm SD card controller registers must be updated to the MCLK domain so subsequent writes to registers will be ignored until 3 clock cycles have passed. This patch adds a 3 clock cycle delay required after writing to controller registers on Qualcomm SOCs. Without this delay all the register writes are not successful, resulting in not detecting cards. The write clock delay is activated by setting up mclk_delayed_writes variable in variant data. Signed-off-by: Srinivas Kandagatla Reviewed-by: Linus Walleij --- drivers/mmc/host/mmci.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 881bb24..1385554 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -67,6 +67,8 @@ static unsigned int fmax = 515633; * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock * @busy_detect: true if busy detection on dat0 is supported * @pwrreg_nopower: bits in MMCIPOWER don't controls ext. power supply + * @mclk_delayed_writes: enable delayed writes to ensure, subsequent updates + * are not ignored. */ struct variant_data { unsigned int clkreg; @@ -83,6 +85,7 @@ struct variant_data { bool pwrreg_clkgate; bool busy_detect; bool pwrreg_nopower; + bool mclk_delayed_writes; }; static struct variant_data variant_arm = { @@ -171,6 +174,12 @@ static struct variant_data variant_qcom = { .datalength_bits = 24, .blksz_datactrl4 = true, .pwrreg_powerup = MCI_PWR_UP, + /* + * On QCom SD card controller, registers must be updated to the + * MCLK domain so subsequent writes to this register will be ignored + * for 3 clk cycles. + */ + .mclk_delayed_writes = true, }; static inline u32 mmci_readl(struct mmci_host *host, u32 off) @@ -181,6 +190,9 @@ static inline u32 mmci_readl(struct mmci_host *host, u32 off) static inline void mmci_writel(struct mmci_host *host, u32 data, u32 off) { writel(data, host->base + off); + + if (host->variant->mclk_delayed_writes) + udelay(DIV_ROUND_UP((3 * USEC_PER_SEC), host->mclk)); } static int mmci_card_busy(struct mmc_host *mmc)