From patchwork Thu May 15 09:36:44 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 30231 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pa0-f70.google.com (mail-pa0-f70.google.com [209.85.220.70]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 0818E20446 for ; Thu, 15 May 2014 09:37:00 +0000 (UTC) Received: by mail-pa0-f70.google.com with SMTP id lj1sf4241072pab.1 for ; Thu, 15 May 2014 02:37:00 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:delivered-to:from:to:cc:subject :date:message-id:in-reply-to:references:sender:precedence:list-id :x-original-sender:x-original-authentication-results:mailing-list :list-post:list-help:list-archive:list-unsubscribe; bh=wKhw4sj4a2zWC9mxeqUhE+OVr/5JFfp1EVTRrhAyPA0=; b=PeOz5FvFm/+k6giGU6leaw9MxrrWu6hPnBa9axR2/nMe+b2d847mVws14nkPAKPt7D HD334SB9or3Ki02E6bdwRkdIehCyHajTjUk4MCkpXbSo4GorO+Bkp8cLRvAt/kFM4EEM E4PL8y/muuVVUUqkSzyM42dnMIVEYtyzLCGyIHctguM2v9cLjit8dilwp5xnOjizdiqd uPgafhhTO0SFs2DgAug6JShBiwlvIdZtgHZVRpFTpBJNp1QLArz9uQoJzwJkzgUxShH9 I9JifX59x0j5pLCurs3Jgc6QHfpQ3DXI3mNTM7v6B10RjPwpYXHFcR0iV6qg7YKoKWWk t7Ww== X-Gm-Message-State: ALoCoQlVcnO3uSMPeEZ3eP3OVRN1i92PKnEN/o2An75hYvGNxY+EXQBzZm44K405N0Dhmqt/E+6p X-Received: by 10.66.173.75 with SMTP id bi11mr4837846pac.4.1400146620387; Thu, 15 May 2014 02:37:00 -0700 (PDT) MIME-Version: 1.0 X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.42.163 with SMTP id c32ls147137qga.49.gmail; Thu, 15 May 2014 02:37:00 -0700 (PDT) X-Received: by 10.58.201.5 with SMTP id jw5mr7566175vec.6.1400146620240; Thu, 15 May 2014 02:37:00 -0700 (PDT) Received: from mail-ve0-f175.google.com (mail-ve0-f175.google.com [209.85.128.175]) by mx.google.com with ESMTPS id v8si837853vcs.68.2014.05.15.02.37.00 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 15 May 2014 02:37:00 -0700 (PDT) Received-SPF: pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.175 as permitted sender) client-ip=209.85.128.175; Received: by mail-ve0-f175.google.com with SMTP id jw12so932132veb.6 for ; Thu, 15 May 2014 02:37:00 -0700 (PDT) X-Received: by 10.52.13.41 with SMTP id e9mr6522046vdc.21.1400146620137; Thu, 15 May 2014 02:37:00 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.221.72 with SMTP id ib8csp307824vcb; Thu, 15 May 2014 02:36:59 -0700 (PDT) X-Received: by 10.66.254.166 with SMTP id aj6mr11184968pad.11.1400146618176; Thu, 15 May 2014 02:36:58 -0700 (PDT) Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id te5si4814069pab.12.2014.05.15.02.36.57; Thu, 15 May 2014 02:36:57 -0700 (PDT) Received-SPF: none (google.com: linux-mmc-owner@vger.kernel.org does not designate permitted sender hosts) client-ip=209.132.180.67; Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753102AbaEOJgw (ORCPT + 6 others); Thu, 15 May 2014 05:36:52 -0400 Received: from mail-wi0-f182.google.com ([209.85.212.182]:43854 "EHLO mail-wi0-f182.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753269AbaEOJgu (ORCPT ); Thu, 15 May 2014 05:36:50 -0400 Received: by mail-wi0-f182.google.com with SMTP id r20so3841394wiv.3 for ; Thu, 15 May 2014 02:36:49 -0700 (PDT) X-Received: by 10.194.120.68 with SMTP id la4mr7562508wjb.40.1400146609220; Thu, 15 May 2014 02:36:49 -0700 (PDT) Received: from srini-ThinkPad-X1-Carbon-2nd.dlink.com (host-78-145-240-98.as13285.net. [78.145.240.98]) by mx.google.com with ESMTPSA id fi2sm32619029wic.15.2014.05.15.02.36.46 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 15 May 2014 02:36:47 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Russell King , Ulf Hansson , linux-mmc@vger.kernel.org Cc: Chris Ball , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linus.walleij@linaro.org, Srinivas Kandagatla Subject: [PATCH v2 04/14] mmc: mmci: Add Qcom datactrl register variant Date: Thu, 15 May 2014 10:36:44 +0100 Message-Id: <1400146604-29970-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1400146447-29803-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1400146447-29803-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-mmc-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-mmc@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: srinivas.kandagatla@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.128.175 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Srinivas Kandagatla Instance of this IP on Qualcomm's SOCs has bit different layout for datactrl register. Bit position datactrl[16:4] hold the true block size instead of power of 2. Signed-off-by: Srinivas Kandagatla Reviewed-by: Linus Walleij --- drivers/mmc/host/mmci.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 7bdf4d3..324a886 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -60,6 +60,8 @@ static unsigned int fmax = 515633; * @sdio: variant supports SDIO * @st_clkdiv: true if using a ST-specific clock divider algorithm * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register + * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl + * register * @pwrreg_powerup: power up value for MMCIPOWER register * @signal_direction: input/out direction of bus signals can be indicated * @pwrreg_clkgate: MMCIPOWER register must be used to gate the clock @@ -75,6 +77,7 @@ struct variant_data { bool sdio; bool st_clkdiv; bool blksz_datactrl16; + bool blksz_datactrl4; u32 pwrreg_powerup; bool signal_direction; bool pwrreg_clkgate; @@ -164,6 +167,7 @@ static struct variant_data variant_qcom = { .fifosize = 16 * 4, .fifohalfsize = 8 * 4, .clkreg = MCI_CLK_ENABLE, + .blksz_datactrl4 = true, .datalength_bits = 24, .blksz_datactrl4 = true, .pwrreg_powerup = MCI_PWR_UP, @@ -740,6 +744,8 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) if (variant->blksz_datactrl16) datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); + else if (variant->blksz_datactrl4) + datactrl = MCI_DPSM_ENABLE | (data->blksz << 4); else datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;