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[78.147.6.229]) by mx.google.com with ESMTPSA id s2sm3474719wia.7.2014.04.29.01.20.21 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Tue, 29 Apr 2014 01:20:21 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: Russell King , linux-mmc@vger.kernel.org Cc: Chris Ball , Ulf Hansson , linux-kernel@vger.kernel.org, agross@quicinc.com, linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH v1 06/11] mmc: mmci: Qcomm: Add 3 clock cycle delay after register write Date: Tue, 29 Apr 2014 09:20:14 +0100 Message-Id: <1398759614-13217-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398759492-12970-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1398759492-12970-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: srinivas.kandagatla@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: patch+caf_=patchwork-forward=linaro.org@linaro.org does not designate permitted sender hosts) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Srinivas Kandagatla Most of the Qcomm SD card controller registers must be updated to the MCLK domain so subsequent writes to registers will be ignored until 3 clock cycles have passed. This patch adds a 3 clock cycle delay required after writing to controller registers on Qualcomm SOCs. Without this delay all the register writes are not successfull, resulting in not detecting cards. Signed-off-by: Srinivas Kandagatla --- drivers/mmc/host/mmci.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 4f8d0ba..f73dc48 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -179,6 +179,14 @@ static inline u32 mmci_readl(struct mmci_host *host, u32 off) static inline void mmci_writel(struct mmci_host *host, u32 data, u32 off) { writel(data, host->base + off); + + /* + * On QCom SD card controller, registers must be updated to the + * MCLK domain so subsequent writes to this register will be ignored + * for 3 clk cycles. + */ + if (host->hw_designer == AMBA_VENDOR_QCOM) + udelay(1 + ((3 * USEC_PER_SEC)/host->mclk)); } static int mmci_card_busy(struct mmc_host *mmc)