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[78.149.8.254]) by mx.google.com with ESMTPSA id hm5sm58833850wjc.17.2014.04.21.14.49.10 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 21 Apr 2014 14:49:10 -0700 (PDT) From: srinivas.kandagatla@linaro.org To: linux-mmc@vger.kernel.org Cc: Russell King , Chris Ball , Ulf Hansson , linux-kernel@vger.kernel.org, agross@quicinc.com, linux-arm-msm@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH RFC 10/12] mmc: mmci: Add clock support for Qualcomm. Date: Mon, 21 Apr 2014 22:49:05 +0100 Message-Id: <1398116945-31640-1-git-send-email-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1398116624-31052-1-git-send-email-srinivas.kandagatla@linaro.org> References: <1398116624-31052-1-git-send-email-srinivas.kandagatla@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: list List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: srinivas.kandagatla@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.174 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , From: Srinivas Kandagatla MCICLK going to card bus is directly driven by the clock controller, so the driver has to set the required rates depending on the state of the card. This bit of support is very much similar to bypass mode but there is no such thing called bypass mode in MCICLK register of Qcom SD card controller. By default the clock is directly driven by the clk controller. This patch adds clock support for Qualcomm SDCC in the driver. This bit of code is conditioned on hw designer. Signed-off-by: Srinivas Kandagatla --- drivers/mmc/host/mmci.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index f465eb5..2cd3a8f 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -291,7 +291,18 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) host->cclk = 0; if (desired) { - if (desired >= host->mclk) { + if (desired != host->mclk && + host->hw_designer == AMBA_VENDOR_QCOM) { + /* Qcom MCLKCLK register does not define bypass bits */ + int rc = clk_set_rate(host->clk, desired); + if (rc < 0) { + dev_err(mmc_dev(host->mmc), + "Error setting clock rate (%d)\n", rc); + } else { + host->mclk = clk_get_rate(host->clk); + host->cclk = host->mclk; + } + } else if (desired >= host->mclk) { clk = MCI_CLK_BYPASS; if (variant->st_clkdiv) clk |= MCI_ST_UX500_NEG_EDGE; @@ -1612,7 +1623,8 @@ static int mmci_probe(struct amba_device *dev, * of course. */ if (plat->f_max) - mmc->f_max = min(host->mclk, plat->f_max); + mmc->f_max = (host->hw_designer == AMBA_VENDOR_QCOM) ? + plat->f_max : min(host->mclk, plat->f_max); else mmc->f_max = min(host->mclk, fmax); dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);