From patchwork Tue Jun 28 07:57:49 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Linus Walleij X-Patchwork-Id: 2337 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id EB1E123F08 for ; Tue, 28 Jun 2011 07:58:08 +0000 (UTC) Received: from mail-qw0-f52.google.com (mail-qw0-f52.google.com [209.85.216.52]) by fiordland.canonical.com (Postfix) with ESMTP id B40ADA18064 for ; Tue, 28 Jun 2011 07:58:08 +0000 (UTC) Received: by mail-qw0-f52.google.com with SMTP id 8so3928081qwb.11 for ; Tue, 28 Jun 2011 00:58:08 -0700 (PDT) Received: by 10.229.62.194 with SMTP id y2mr5486302qch.4.1309247886826; Tue, 28 Jun 2011 00:58:06 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.229.48.135 with SMTP id r7cs1851qcf; Tue, 28 Jun 2011 00:58:06 -0700 (PDT) Received: by 10.14.22.13 with SMTP id s13mr4605228ees.89.1309247885363; Tue, 28 Jun 2011 00:58:05 -0700 (PDT) Received: from eu1sys200aog117.obsmtp.com (eu1sys200aog117.obsmtp.com [207.126.144.143]) by mx.google.com with SMTP id h33si10872443eeb.12.2011.06.28.00.57.57 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 28 Jun 2011 00:58:05 -0700 (PDT) Received-SPF: neutral (google.com: 207.126.144.143 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) client-ip=207.126.144.143; Authentication-Results: mx.google.com; spf=neutral (google.com: 207.126.144.143 is neither permitted nor denied by best guess record for domain of linus.walleij@stericsson.com) smtp.mail=linus.walleij@stericsson.com Received: from beta.dmz-ap.st.com ([138.198.100.35]) (using TLSv1) by eu1sys200aob117.postini.com ([207.126.147.11]) with SMTP ID DSNKTgmJhMROwUEKX0qHjzeAH/5TV1vsnDns@postini.com; Tue, 28 Jun 2011 07:58:04 UTC Received: from zeta.dmz-ap.st.com (ns6.st.com [138.198.234.13]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 24D20F4; Tue, 28 Jun 2011 07:57:54 +0000 (GMT) Received: from relay1.stm.gmessaging.net (unknown [10.230.100.17]) by zeta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 83C1B96D; Tue, 28 Jun 2011 07:57:53 +0000 (GMT) Received: from exdcvycastm003.EQ1STM.local (alteon-source-exch [10.230.100.61]) (using TLSv1 with cipher RC4-MD5 (128/128 bits)) (Client CN "exdcvycastm003", Issuer "exdcvycastm003" (not verified)) by relay1.stm.gmessaging.net (Postfix) with ESMTPS id 2D4C924C2F2; Tue, 28 Jun 2011 09:57:48 +0200 (CEST) Received: from localhost.localdomain (10.230.100.153) by smtp.stericsson.com (10.230.100.1) with Microsoft SMTP Server (TLS) id 8.3.83.0; Tue, 28 Jun 2011 09:57:52 +0200 From: Linus Walleij To: , Cc: Lee Jones , Ulf Hansson , Dmitry Tarnyagin , Linus Walleij Subject: [PATCH 4/4] mmci: fixup sg buffer handling in pio_write Date: Tue, 28 Jun 2011 09:57:49 +0200 Message-ID: <1309247869-17220-1-git-send-email-linus.walleij@stericsson.com> X-Mailer: git-send-email 1.7.3.2 MIME-Version: 1.0 From: Ulf Hansson Earlier code in pio_write was expecting that each scatter-gather buffer was 4-bytes aligned which is not always the case, especially when dealing with long chains of SDIO packages. This patch fix the problem by using a 4 bytes buffer to cache unaligned data between each unaligned pio_write operation. In the last transaction we pad the last write access with zeroes. Remove older fix for ST Micro since it was not a variant-specific problem. Signed-off-by: Ulf Hansson Reviewed-by: Henrik Carling Signed-off-by: Dmitry Tarnyagin [Minor fixups like making the cache word a u32] Signed-off-by: Linus Walleij --- drivers/mmc/host/mmci.c | 106 ++++++++++++++++++++++++++++++++++------------ drivers/mmc/host/mmci.h | 3 + 2 files changed, 81 insertions(+), 28 deletions(-) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index 93dcd2a..81aac79 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -533,6 +533,8 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) host->size = data->blksz * data->blocks; host->dataend = false; data->bytes_xfered = 0; + host->cache_len = 0; + host->cache = 0; clks = (unsigned long long)data->timeout_ns * host->cclk; do_div(clks, 1000000000UL); @@ -712,43 +714,88 @@ static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int rem struct variant_data *variant = host->variant; void __iomem *base = host->base; char *ptr = buffer; + unsigned int data_left = host->size; + unsigned int count, maxcnt; + char *cache_ptr; + int i; do { - unsigned int count, maxcnt; - maxcnt = status & MCI_TXFIFOEMPTY ? variant->fifosize : variant->fifohalfsize; - count = min(remain, maxcnt); /* - * The ST Micro variant for SDIO transfer sizes - * less then 8 bytes should have clock H/W flow - * control disabled. + * A write to the FIFO must always be done of 4 bytes aligned + * data. If the buffer is not 4 bytes aligned we must pad the + * data, but this must only be done for the final write for the + * entire data transfer, otherwise we will corrupt the data. + * Thus a buffer cache of four bytes is needed to temporary + * store data. */ - if (variant->sdio && - mmc_card_sdio(host->mmc->card)) { - if (count < 8) - writel(readl(host->base + MMCICLOCK) & - ~variant->clkreg_enable, - host->base + MMCICLOCK); - else - writel(readl(host->base + MMCICLOCK) | - variant->clkreg_enable, - host->base + MMCICLOCK); + if (host->cache_len) { + cache_ptr = (char *)&host->cache; + cache_ptr = cache_ptr + host->cache_len; + data_left += host->cache_len; + + while ((host->cache_len < 4) && (remain > 0)) { + *cache_ptr = *ptr; + cache_ptr++; + ptr++; + host->cache_len++; + remain--; + } + + if ((host->cache_len == 4) || + (data_left == host->cache_len)) { + + writesl(base + MMCIFIFO, &host->cache, 1); + if (data_left == host->cache_len) + break; + + host->cache = 0; + host->cache_len = 0; + maxcnt -= 4; + data_left -= 4; + } + + if (remain == 0) + break; } - /* - * SDIO especially may want to send something that is - * not divisible by 4 (as opposed to card sectors - * etc), and the FIFO only accept full 32-bit writes. - * So compensate by adding +3 on the count, a single - * byte become a 32bit write, 7 bytes will be two - * 32bit writes etc. - */ - writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); + count = min(remain, maxcnt); - ptr += count; - remain -= count; + if (!(count % 4) || (data_left == count)) { + /* + * The data is either 4-bytes aligned or it is the + * last data to write. It is thus fine to potentially + * pad the data if needed. + */ + writesl(base + MMCIFIFO, ptr, (count + 3) >> 2); + ptr += count; + remain -= count; + data_left -= count; + + } else { + + host->cache_len = count % 4; + count = (count >> 2) << 2; + + if (count) + writesl(base + MMCIFIFO, ptr, count >> 2); + + ptr += count; + remain -= count; + data_left -= count; + + i = 0; + cache_ptr = (char *)&host->cache; + while (i < host->cache_len) { + *cache_ptr = *ptr; + cache_ptr++; + ptr++; + remain--; + i++; + } + } if (remain == 0) break; @@ -803,7 +850,10 @@ static irqreturn_t mmci_pio_irq(int irq, void *dev_id) if (status & MCI_TXACTIVE) len = mmci_pio_write(host, buffer, remain, status); - sg_miter->consumed = len; + if (len > sg_miter->consumed) + len = sg_miter->consumed; + else + sg_miter->consumed = len; host->size -= len; remain -= len; diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h index 79156a0..ff93a9c 100644 --- a/drivers/mmc/host/mmci.h +++ b/drivers/mmc/host/mmci.h @@ -196,6 +196,9 @@ struct mmci_host { /* pio stuff */ struct sg_mapping_iter sg_miter; unsigned int size; + u32 cache; + unsigned int cache_len; + struct regulator *vcc; /* sync of DATAEND irq */