From patchwork Sun Sep 29 07:44:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?QW5keS1sZCBMdSAo5Y2i5LicKQ==?= X-Patchwork-Id: 831768 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9F6918C3E; Sun, 29 Sep 2024 07:46:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727595982; cv=none; b=nF6k5BeOzIy6OkoDfM1TlJqs+U/VsT71UbhAQ/UihxR+vtWGn2lzzLrNfNDOlwfjgBUqXCkfp2ofstAsIufodsfnXqpVOn995lDoFQ+CAPGVyOtp12MWs/smv0+uiT1enTQbvOs9F/il/j+U84jJZWwX4FsZqwPT0HmcGe3xCUk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727595982; c=relaxed/simple; bh=vbWrw/gqCIdcm6xt/nYYymwi/IMuYpY2RklLNQyxA8A=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=mb4agQ3ek2Kt2gEmmg4gMEl+88H99ybN03TbUAue6B83rPmCsbwznw4HmzJpBu/+CKtFeIBHCKdJWMfbU+vKjLhtAg9PT2uLqA8iWLTYUFEHWSdGLVTKqToZ4sNjkawkSkrXjR/UviyMredSfRJYnNGzm7LDNV6lrGqejexfXKc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=GAT1U+L3; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="GAT1U+L3" X-UUID: e7b9b79c7e3611ef8b96093e013ec31c-20240929 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=STXCOfMr88bze3bpw9ORgaFnaHy/N/l30mbf79iV5nA=; b=GAT1U+L3zSmujkwyli3YM7z1A5Jfsd1Xcpyn1xXPmyO+qChA7bQDK6iTu00TRftW+F7MBiU2zGIuDFJob71lcWk9UZfIW6dnVq1XveWNoP2CJDhDjWYu+lrsBPoPorY6oAPyylNaUMry9dLRLxefB0HtJCNcKjClNlZMWqXF+AA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.41, REQID:dfcb7fd5-9121-44b5-bbd4-d42295a80905, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6dc6a47, CLOUDID:6638ba9e-8e9a-4ac1-b510-390a86b53c0a, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1, SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULS X-UUID: e7b9b79c7e3611ef8b96093e013ec31c-20240929 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1567370212; Sun, 29 Sep 2024 15:46:15 +0800 Received: from mtkmbs13n1.mediatek.inc (172.21.101.193) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Sun, 29 Sep 2024 15:46:14 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs13n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Sun, 29 Sep 2024 15:46:13 +0800 From: Andy-ld Lu To: , , , , , CC: , , , , , Andy-ld Lu Subject: [PATCH v2 0/2] Add mtk-sd support for MT8196 Date: Sun, 29 Sep 2024 15:44:04 +0800 Message-ID: <20240929074558.2076-1-andy-ld.lu@mediatek.com> X-Mailer: git-send-email 2.46.0 Precedence: bulk X-Mailing-List: linux-mmc@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 There are some new features for Mediatek SoC MT8196, which include new command/data transmitting and receiving path (abbreviated as tx/rx), and two modified register settings. The driver code has to be adapted to implement the above changes, and the compatible string 'mediatek,mt8196-mmc' is added to driver and devicetree bindings. --- Changes in v2: - Use compatible string 'mediatek,mt8196-mmc' to replace 'mediatek,msdc-v2'; - Remove the 'mediatek,stop-dly-sel', 'mediatek,pop-en-cnt' and 'mediatek, prohibit-gate-cg' in devicetree bindings, due to SoC dependent; - Add 'stop_dly_sel' and 'pop_en_cnt' to the compatiblity structure for different register settings; - The SoC's upgraded version would discard the bus design that detect source clock CG when the CPU access the IP registers, so drop the related control flow with 'prohibit_gate_cg' flag. Link to v1: https://patchwork.kernel.org/patch/13812924 --- Andy-ld Lu (2): mmc: mtk-sd: Add support for MT8196 dt-bindings: mmc: mtk-sd: Add support for MT8196 .../devicetree/bindings/mmc/mtk-sd.yaml | 2 + drivers/mmc/host/mtk-sd.c | 162 +++++++++++++++--- 2 files changed, 143 insertions(+), 21 deletions(-)