| Message ID | 20240908102018.3711527-1-avri.altman@wdc.com |
|---|---|
| Headers | show |
| Series | Add SDUC Support | expand |
On 9/8/24 11:20, Avri Altman wrote: > Prevent Host Software Queue from enabling for SDUC. In SDUC, CMD44 is > modified to include 6-bit upper address by utilizing its reserved bits. > Exclude hsq for SDUC for now. The message here is misleading, actually hsq has nothing to do with the actual CQ as in CMD44, it's just a hack to present itself to the mmc subsystem as such to then get more in-flight requests from mmc core, which can be prepared in advance and be issued asynchronously to the completion of the preceding request (in atomic context). So the card is completely oblivious to hsq. This is presumably broken though by the mandatory CMD22 for SDUC. > > Signed-off-by: Avri Altman <avri.altman@wdc.com> > --- > drivers/mmc/core/sd.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c > index 1d09f0f2e769..5d35fc8802c7 100644 > --- a/drivers/mmc/core/sd.c > +++ b/drivers/mmc/core/sd.c > @@ -1558,7 +1558,7 @@ static int mmc_sd_init_card(struct mmc_host *host, u32 ocr, > goto free_card; > } > > - if (host->cqe_ops && !host->cqe_enabled) { > + if (!mmc_card_ult_capacity(card) && host->cqe_ops && !host->cqe_enabled) { > err = host->cqe_ops->cqe_enable(host, card); > if (!err) { > host->cqe_enabled = true;
> On 9/8/24 11:20, Avri Altman wrote: > > Prevent Host Software Queue from enabling for SDUC. In SDUC, CMD44 is > > modified to include 6-bit upper address by utilizing its reserved bits. > > Exclude hsq for SDUC for now. > > The message here is misleading, actually hsq has nothing to do with the actual CQ > as in CMD44, it's just a hack to present itself to the mmc subsystem as such to > then get more in-flight requests from mmc core, which can be prepared in > advance and be issued asynchronously to the completion of the preceding > request (in atomic context). So the card is completely oblivious to hsq. > This is presumably broken though by the mandatory CMD22 for SDUC. Thanks. Somehow, I thought that hsq relies on hw command queue engine. If totally necessary, I will fix it in the next spin. Thanks, Avri > > > > > Signed-off-by: Avri Altman <avri.altman@wdc.com> > > --- > > drivers/mmc/core/sd.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index > > 1d09f0f2e769..5d35fc8802c7 100644 > > --- a/drivers/mmc/core/sd.c > > +++ b/drivers/mmc/core/sd.c > > @@ -1558,7 +1558,7 @@ static int mmc_sd_init_card(struct mmc_host *host, > u32 ocr, > > goto free_card; > > } > > > > - if (host->cqe_ops && !host->cqe_enabled) { > > + if (!mmc_card_ult_capacity(card) && host->cqe_ops && > > + !host->cqe_enabled) { > > err = host->cqe_ops->cqe_enable(host, card); > > if (!err) { > > host->cqe_enabled = true;
On 8/09/24 13:20, Avri Altman wrote: > Ultra Capacity SD cards (SDUC) was already introduced in SD7.0. Those > cards support capacity larger than 2TB and up to including 128TB. Thus, > the address range of the card expands beyond the 32-bit command > argument. To that end, a new command - CMD22 is defined, to carry the > extra 6-bit upper part of the 38-bit block address that enable access to > 128TB memory space. > > SDUC capacity is agnostic to the interface mode: UHS-I and UHS-II – Same > as SDXC. > > The spec defines several extensions/modifications to the current SDXC > cards, which we address in patches 1 - 10. Otherwise requirements are > out-of-scope of this change. Specifically, CMDQ (CMD44+CMD45), and > Extension for Video Speed Class (CMD20). > > First publication of SDUC was in [1]. This series was developed and > tested separately from [1] and does not borrow from it. > > [1] https://lwn.net/Articles/982566/ I didn't actually give my Reviewed-by in v6, but I guess it can stand for those patches. For "mmc: core: Prevent HSQ from enabling for SDUC" it needs feedback from HSQ users - cc'ed Michael Wu and Wenchao Chen Otherwise I have no further comments for now. > > --- > Changes in v7: > - Minimizes the padding further in mmc_command (Christian) > - Set the SD_OCR_2T when enabling SDUC (Adrian) > - Remove unnecessary casting (Adrian) > - Remove redundant else and switch patches 3 & 4 (Adrian) > - Add patch to prevent HSQ from enabling (Adrian) > - Remove redundant variable and make use of clamp_val (Adrian) > > Changes in v6: > - Remove Ricky's tested-by tag - the series has changed greatly > - Call mmc_send_ext_addr from mmc_start_request (Adrian) > > Changes in v5: > - leave out the mask in mmc_send_ext_addr (Adrian) > - leave out close-ended SDUC support > - remove 500msec write delay as there is no busy indication (Adrian) > - disable mmc-test for SDUC > - move enabling SDUC to the last patch (Adrian) > > Changes in v4: > - Squash patches 1 & 2 (Ulf) > - Amend SD_OCR_2T to SD_OCR_CCS in mmc_sd_get_cid (Ulf) > - Use card state instead of caps2 (Ricky & Ulf) > - Switch patches 5 & 6 (Ulf) > > Changes in v3: > - Some more kernel test robot fixes > - Fix a typo in a commit log (Ricky WU) > - Fix ACMD22 returned value > - Add 'Tested-by' tag for the whole series (Ricky WU) > > Changes in v2: > - Attend kernel test robot warnings > > --- > > Avri Altman (10): > mmc: sd: SDUC Support Recognition > mmc: sd: Add Extension memory addressing > mmc: core: Don't use close-ended rw for SDUC > mmc: core: Add open-ended Ext memory addressing > mmc: core: Allow mmc erase to carry large addresses > mmc: core: Add Ext memory addressing for erase > mmc: core: Adjust ACMD22 to SDUC > mmc: core: Disable SDUC for mmc_test > mmc: core: Prevent HSQ from enabling for SDUC > mmc: core: Enable SDUC > > drivers/mmc/core/block.c | 37 +++++++++++++++++++++------- > drivers/mmc/core/bus.c | 4 +++- > drivers/mmc/core/card.h | 3 +++ > drivers/mmc/core/core.c | 48 +++++++++++++++++++++++++------------ > drivers/mmc/core/core.h | 16 +++++++++---- > drivers/mmc/core/mmc_test.c | 6 +++++ > drivers/mmc/core/sd.c | 38 +++++++++++++++++++---------- > drivers/mmc/core/sd.h | 2 +- > drivers/mmc/core/sd_ops.c | 16 +++++++++++++ > drivers/mmc/core/sd_ops.h | 1 + > drivers/mmc/core/sdio.c | 2 +- > include/linux/mmc/card.h | 2 +- > include/linux/mmc/core.h | 5 ++++ > include/linux/mmc/sd.h | 4 ++++ > 14 files changed, 139 insertions(+), 45 deletions(-) >
> I didn't actually give my Reviewed-by in v6, but I guess it can stand for those > patches. Sorry about that - apparently, I misunderstood your last comment to v6 0/9 > > For "mmc: core: Prevent HSQ from enabling for SDUC" it needs feedback from > HSQ users - cc'ed Michael Wu and Wenchao Chen > > Otherwise I have no further comments for now. Thanks. Ulf, Am I expected to do something more? Thanks, Avri
On Tue, 10 Sept 2024 at 12:56, Avri Altman <Avri.Altman@wdc.com> wrote: > > > I didn't actually give my Reviewed-by in v6, but I guess it can stand for those > > patches. > Sorry about that - apparently, I misunderstood your last comment to v6 0/9 > > > > > For "mmc: core: Prevent HSQ from enabling for SDUC" it needs feedback from > > HSQ users - cc'ed Michael Wu and Wenchao Chen > > > > Otherwise I have no further comments for now. > Thanks. > > Ulf, > Am I expected to do something more? No, I just need some more time to review this, sorry. I am also heading to LPC next week, so hopefully I will get to review the series before that... Kind regards Uffe
> > Ulf, > > Am I expected to do something more? > > No, I just need some more time to review this, sorry. > > I am also heading to LPC next week, so hopefully I will get to review the series > before that... A gentle ping. Thanks, Avri > > Kind regards > Uffe
> > > Ulf, > > > Am I expected to do something more? > > > > No, I just need some more time to review this, sorry. > > > > I am also heading to LPC next week, so hopefully I will get to review > > the series before that... > A gentle ping. Another one. Thanks, Avri
On Sun, 8 Sept 2024 at 14:11, Avri Altman <Avri.Altman@wdc.com> wrote: > > > On 9/8/24 11:20, Avri Altman wrote: > > > Prevent Host Software Queue from enabling for SDUC. In SDUC, CMD44 is > > > modified to include 6-bit upper address by utilizing its reserved bits. > > > Exclude hsq for SDUC for now. > > > > The message here is misleading, actually hsq has nothing to do with the actual CQ > > as in CMD44, it's just a hack to present itself to the mmc subsystem as such to > > then get more in-flight requests from mmc core, which can be prepared in > > advance and be issued asynchronously to the completion of the preceding > > request (in atomic context). So the card is completely oblivious to hsq. > > This is presumably broken though by the mandatory CMD22 for SDUC. > Thanks. > Somehow, I thought that hsq relies on hw command queue engine. > If totally necessary, I will fix it in the next spin. I suggest we at least update the commit message so we understand why we don't allow hsq for SDUC. It seems possible to make it work for hsq, but I don't mind if we consider that as an improvement on top of the initial support for SDUC. Does that make sense? [...] Kind regards Uffe
On Tue, 1 Oct 2024 at 09:03, Avri Altman <Avri.Altman@wdc.com> wrote: > > > > > Ulf, > > > > Am I expected to do something more? > > > > > > No, I just need some more time to review this, sorry. > > > > > > I am also heading to LPC next week, so hopefully I will get to review > > > the series before that... > > A gentle ping. > Another one. Thanks for pinging and my apologies for the long delay! I have looked through the series and provided you with a few comments, mostly very minor things. That said, I have no further comments and will be awaiting a new and final version from you that I can apply. Kind regards Uffe
> On Tue, 1 Oct 2024 at 09:03, Avri Altman <Avri.Altman@wdc.com> wrote: > > > > > > > Ulf, > > > > > Am I expected to do something more? > > > > > > > > No, I just need some more time to review this, sorry. > > > > > > > > I am also heading to LPC next week, so hopefully I will get to > > > > review the series before that... > > > A gentle ping. > > Another one. > > Thanks for pinging and my apologies for the long delay! > > I have looked through the series and provided you with a few comments, > mostly very minor things. That said, I have no further comments and will be > awaiting a new and final version from you that I can apply. Thanks. Will make the required corrections and send it next week. Thanks, Avri > > Kind regards > Uffe
> On Sun, 8 Sept 2024 at 14:11, Avri Altman <Avri.Altman@wdc.com> wrote: > > > > > On 9/8/24 11:20, Avri Altman wrote: > > > > Prevent Host Software Queue from enabling for SDUC. In SDUC, CMD44 > > > > is modified to include 6-bit upper address by utilizing its reserved bits. > > > > Exclude hsq for SDUC for now. > > > > > > The message here is misleading, actually hsq has nothing to do with > > > the actual CQ as in CMD44, it's just a hack to present itself to the > > > mmc subsystem as such to then get more in-flight requests from mmc > > > core, which can be prepared in advance and be issued asynchronously > > > to the completion of the preceding request (in atomic context). So the > card is completely oblivious to hsq. > > > This is presumably broken though by the mandatory CMD22 for SDUC. > > Thanks. > > Somehow, I thought that hsq relies on hw command queue engine. > > If totally necessary, I will fix it in the next spin. > > I suggest we at least update the commit message so we understand why we > don't allow hsq for SDUC. It seems possible to make it work for hsq, but I > don't mind if we consider that as an improvement on top of the initial > support for SDUC. > > Does that make sense? Yes. Will do. Thanks, Avri > > [...] > > Kind regards > Uffe