| Message ID | 20220504213251.264819-1-sebastian.reichel@collabora.com |
|---|---|
| Headers | show |
| Series | Basic RK3588 Support | expand |
Hi, On Thu, May 05, 2022 at 03:51:25PM +0200, Nicolas Frattaroli wrote: > On Mittwoch, 4. Mai 2022 23:32:43 CEST Sebastian Reichel wrote: > > From: Jianqun Xu <jay.xu@rock-chips.com> > > > > Add pinctrl support for RK3588. > > > > Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> > > [merged in downstream fixes, simplified register lookup logic for better > > maintanence at the cost of a bit more static const memory and fixed some > > incorrect registers] > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > > Hi, > > a heads up to the maintainer: this was already merged. The cover letter > states > > > * Dropped pinctrl and mmc binding patch (applied) > > so I think this was included by accident. I missed that the driver patch also has been merged (cover letter was just about the binding patches). Apparently I also accidently forgot to skip the first two patches, so they are not dropped but just moved to the beginning :( -- Sebastian
Hi, On Wed, May 04, 2022 at 11:32:32PM +0200, Sebastian Reichel wrote: > Add compatible value for the Rockchip rk3588 dwcmshc controller. > > Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- This patch has already been applied, but I accidently resend it. Please ignore it. -- Sebastian > Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml > index f300ced4cdf3..71f8e726d641 100644 > --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml > +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml > @@ -17,6 +17,7 @@ properties: > compatible: > enum: > - rockchip,rk3568-dwcmshc > + - rockchip,rk3588-dwcmshc > - snps,dwcmshc-sdhci > > reg: > -- > 2.35.1 >
On Wed, 04 May 2022 23:32:46 +0200, Sebastian Reichel wrote: > Add IOC and PHP GRF syscon compatibles for RK3588. > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
On Wed, 04 May 2022 23:32:47 +0200, Sebastian Reichel wrote: > Allow usage of gpio-ranges with the rockchip gpio controller. The driver > already had support for this since it has been added to the mainline kernel > in the first place. > > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> > --- > Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml | 2 ++ > 1 file changed, 2 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
On Wed, 4 May 2022 at 23:33, Sebastian Reichel <sebastian.reichel@collabora.com> wrote: > > Prepare driver for rk3588 support by renaming the internal data > structures. > > Acked-by: Adrian Hunter <adrian.hunter@intel.com> > Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Queued for v5.20 on the devel branch, thanks! Kind regards Uffe > --- > drivers/mmc/host/sdhci-of-dwcmshc.c | 46 ++++++++++++++--------------- > 1 file changed, 23 insertions(+), 23 deletions(-) > > diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c > index 3a1b5ba36405..f5fd88c7adef 100644 > --- a/drivers/mmc/host/sdhci-of-dwcmshc.c > +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c > @@ -56,14 +56,14 @@ > #define DLL_LOCK_WO_TMOUT(x) \ > ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ > (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) > -#define RK3568_MAX_CLKS 3 > +#define RK35xx_MAX_CLKS 3 > > #define BOUNDARY_OK(addr, len) \ > ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) > > -struct rk3568_priv { > +struct rk35xx_priv { > /* Rockchip specified optional clocks */ > - struct clk_bulk_data rockchip_clks[RK3568_MAX_CLKS]; > + struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS]; > struct reset_control *reset; > u8 txclk_tapnum; > }; > @@ -178,7 +178,7 @@ static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock > { > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); > - struct rk3568_priv *priv = dwc_priv->priv; > + struct rk35xx_priv *priv = dwc_priv->priv; > u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; > u32 extra, reg; > int err; > @@ -281,7 +281,7 @@ static const struct sdhci_ops sdhci_dwcmshc_ops = { > .adma_write_desc = dwcmshc_adma_write_desc, > }; > > -static const struct sdhci_ops sdhci_dwcmshc_rk3568_ops = { > +static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { > .set_clock = dwcmshc_rk3568_set_clock, > .set_bus_width = sdhci_set_bus_width, > .set_uhs_signaling = dwcmshc_set_uhs_signaling, > @@ -296,18 +296,18 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { > .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, > }; > > -static const struct sdhci_pltfm_data sdhci_dwcmshc_rk3568_pdata = { > - .ops = &sdhci_dwcmshc_rk3568_ops, > +static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { > + .ops = &sdhci_dwcmshc_rk35xx_ops, > .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | > SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, > .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | > SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, > }; > > -static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) > +static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) > { > int err; > - struct rk3568_priv *priv = dwc_priv->priv; > + struct rk35xx_priv *priv = dwc_priv->priv; > > priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); > if (IS_ERR(priv->reset)) { > @@ -319,14 +319,14 @@ static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc > priv->rockchip_clks[0].id = "axi"; > priv->rockchip_clks[1].id = "block"; > priv->rockchip_clks[2].id = "timer"; > - err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK3568_MAX_CLKS, > + err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS, > priv->rockchip_clks); > if (err) { > dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err); > return err; > } > > - err = clk_bulk_prepare_enable(RK3568_MAX_CLKS, priv->rockchip_clks); > + err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks); > if (err) { > dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err); > return err; > @@ -348,7 +348,7 @@ static int dwcmshc_rk3568_init(struct sdhci_host *host, struct dwcmshc_priv *dwc > static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { > { > .compatible = "rockchip,rk3568-dwcmshc", > - .data = &sdhci_dwcmshc_rk3568_pdata, > + .data = &sdhci_dwcmshc_rk35xx_pdata, > }, > { > .compatible = "snps,dwcmshc-sdhci", > @@ -371,7 +371,7 @@ static int dwcmshc_probe(struct platform_device *pdev) > struct sdhci_pltfm_host *pltfm_host; > struct sdhci_host *host; > struct dwcmshc_priv *priv; > - struct rk3568_priv *rk_priv = NULL; > + struct rk35xx_priv *rk_priv = NULL; > const struct sdhci_pltfm_data *pltfm_data; > int err; > u32 extra; > @@ -426,8 +426,8 @@ static int dwcmshc_probe(struct platform_device *pdev) > host->mmc_host_ops.request = dwcmshc_request; > host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; > > - if (pltfm_data == &sdhci_dwcmshc_rk3568_pdata) { > - rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk3568_priv), GFP_KERNEL); > + if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) { > + rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL); > if (!rk_priv) { > err = -ENOMEM; > goto err_clk; > @@ -435,7 +435,7 @@ static int dwcmshc_probe(struct platform_device *pdev) > > priv->priv = rk_priv; > > - err = dwcmshc_rk3568_init(host, priv); > + err = dwcmshc_rk35xx_init(host, priv); > if (err) > goto err_clk; > } > @@ -452,7 +452,7 @@ static int dwcmshc_probe(struct platform_device *pdev) > clk_disable_unprepare(pltfm_host->clk); > clk_disable_unprepare(priv->bus_clk); > if (rk_priv) > - clk_bulk_disable_unprepare(RK3568_MAX_CLKS, > + clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, > rk_priv->rockchip_clks); > free_pltfm: > sdhci_pltfm_free(pdev); > @@ -464,14 +464,14 @@ static int dwcmshc_remove(struct platform_device *pdev) > struct sdhci_host *host = platform_get_drvdata(pdev); > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); > - struct rk3568_priv *rk_priv = priv->priv; > + struct rk35xx_priv *rk_priv = priv->priv; > > sdhci_remove_host(host, 0); > > clk_disable_unprepare(pltfm_host->clk); > clk_disable_unprepare(priv->bus_clk); > if (rk_priv) > - clk_bulk_disable_unprepare(RK3568_MAX_CLKS, > + clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, > rk_priv->rockchip_clks); > sdhci_pltfm_free(pdev); > > @@ -484,7 +484,7 @@ static int dwcmshc_suspend(struct device *dev) > struct sdhci_host *host = dev_get_drvdata(dev); > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); > - struct rk3568_priv *rk_priv = priv->priv; > + struct rk35xx_priv *rk_priv = priv->priv; > int ret; > > ret = sdhci_suspend_host(host); > @@ -496,7 +496,7 @@ static int dwcmshc_suspend(struct device *dev) > clk_disable_unprepare(priv->bus_clk); > > if (rk_priv) > - clk_bulk_disable_unprepare(RK3568_MAX_CLKS, > + clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, > rk_priv->rockchip_clks); > > return ret; > @@ -507,7 +507,7 @@ static int dwcmshc_resume(struct device *dev) > struct sdhci_host *host = dev_get_drvdata(dev); > struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); > struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); > - struct rk3568_priv *rk_priv = priv->priv; > + struct rk35xx_priv *rk_priv = priv->priv; > int ret; > > ret = clk_prepare_enable(pltfm_host->clk); > @@ -521,7 +521,7 @@ static int dwcmshc_resume(struct device *dev) > } > > if (rk_priv) { > - ret = clk_bulk_prepare_enable(RK3568_MAX_CLKS, > + ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, > rk_priv->rockchip_clks); > if (ret) > return ret; > -- > 2.35.1 >
Hi, This patchset adds initial rudimentary support for the rk3588 SoC using Rockchip's evaluation board for platform bringup. With this patchset it is possible to boot into stock Debian, if it has been previously installed on the eMMC in some way (e.g. pre-installed vendor OS) using the Debug UART as interface. Apart from the eMMC, the CPUs and the UART nothing works and will be added separately on top step-by-step. The patch series is based on v5.18-rc1. This has been sent as a series, since all bits are required for testing on real HW. It should be fine to merge the mmc, gpio and pinctrl bits via their own trees. Both, the DT and the clock driver require the shared include/dt-bindings/clock/rk3588-cru.h, so that requires some coordination. Changelog since PATCHv1: * https://lore.kernel.org/all/20220422170920.401914-1-sebastian.reichel@collabora.com/ * Fix cover letter to correctly reference 5.18-rc1 last one had a typo mentioning 4.18-rc1 (Emil Velikov) * Fix title in CRU binding (Krzysztof Kozlowski) * Replace status "ok" with "okay" (Krzysztof Kozlowski) * Remove simple-bus for clocks and rename clock nodes (Krzysztof Kozlowski) * Remove ITS from GIC controller, since the current mainline GIC kernel driver cannot handle the rockchip shareability quirk. Instead use MBI like the rk356x platform does at the moment. (Robin Murphy) * With the previous change it is possible to describe the full CPU cluster; for now without operating-point support, which requires additional cpufreq changes / rockchip specific driver (Robin Murphy) * Remove GIC_CPU_MASK_SIMPLE(4) from armv8-timer (Robin Murphy) * Add pmu node for A76 * Move interrupt-affinity configuration into gic, which has only one cluster configured for all CPU cores * Fix sdhci-of-dwcmshc reset code to make reset control optional, since old rk356x DT does not describe it (Dmitry Osipenko) * Modify sdhci-of-dwcmshc, so that dwcmshc_rk35xx_postinit is called between sdhci_setup_host() and __sdhci_add_host() (Adrian Hunter) * Checked if 'allOf:if:then:' needs changes for rk3588 and none are required yet. RK3588 has more syscon nodes and they will need changes once support for them is added (Krzysztof Kozlowski) * Move SCMI_HCLK_SD definition into correct patch (Rob Herring) * Fix warnings found by kernel test robot * Add patch to document gpio-ranges in the rockchip gpio-bank to fix warnings from dtbs_check * Update PLL in the CRU, so that it fully relies on lookup tables instead of calculating required PLL parameters for arbitrary frequencies (Nicolas Dufresne & Heiko Stübner) * Collected Acks * Dropped pinctrl and mmc binding patch (applied) -- Sebastian Elaine Zhang (6): dt-binding: clock: Document rockchip,rk3588-cru bindings clk: rockchip: add register offset of the cores select parent clk: rockchip: add pll type for RK3588 clk: rockchip: clk-cpu: add mux setting for cpu change frequency clk: rockchip: add dt-binding header for rk3588 clk: rockchip: Add clock controller for the RK3588 Jianqun Xu (3): pinctrl/rockchip: add rk3588 support gpio: rockchip: add support for rk3588 arm64: dts: rockchip: Add rk3588s pinctrl data Kever Yang (2): arm64: dts: rockchip: Add base DT for rk3588 SoC arm64: dts: rockchip: Add rk3588-evb1 board Sebastian Reichel (8): dt-bindings: pinctrl: rockchip: add rk3588 dt-bindings: mmc: sdhci-of-dwcmhsc: Add rk3588 mmc: sdhci-of-dwcmshc: rename rk3568 to rk35xx pinctrl/rockchip: add error handling for pull/drive register getters dt-bindings: serial: snps-dw-apb-uart: Add Rockchip RK3588 dt-bindings: soc: rockchip: add initial rk3588 syscon compatibles dt-bindings: gpio: rockchip: add gpio-ranges dt-bindings: pinctrl: rockchip: increase max amount of device functions Yifeng Zhao (2): mmc: sdhci-of-dwcmshc: add reset call back for rockchip Socs mmc: sdhci-of-dwcmshc: add support for rk3588 .../devicetree/bindings/arm/rockchip.yaml | 5 + .../bindings/clock/rockchip,rk3588-cru.yaml | 63 + .../bindings/gpio/rockchip,gpio-bank.yaml | 2 + .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 1 + .../bindings/pinctrl/rockchip,pinctrl.yaml | 3 +- .../bindings/serial/snps-dw-apb-uart.yaml | 1 + .../devicetree/bindings/soc/rockchip/grf.yaml | 2 + arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3588-evb1-v10.dts | 34 + arch/arm64/boot/dts/rockchip/rk3588.dtsi | 6 + .../boot/dts/rockchip/rk3588s-pinctrl.dtsi | 3403 +++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 719 ++++ drivers/clk/rockchip/Kconfig | 7 + drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk-cpu.c | 69 +- drivers/clk/rockchip/clk-pll.c | 218 +- drivers/clk/rockchip/clk-rk3588.c | 2497 ++++++++++++ drivers/clk/rockchip/clk.h | 65 + drivers/gpio/gpio-rockchip.c | 3 +- drivers/mmc/host/sdhci-of-dwcmshc.c | 193 +- drivers/pinctrl/pinctrl-rockchip.c | 468 ++- drivers/pinctrl/pinctrl-rockchip.h | 170 +- include/dt-bindings/clock/rk3588-cru.h | 1492 ++++++++ 23 files changed, 9306 insertions(+), 117 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts create mode 100644 arch/arm64/boot/dts/rockchip/rk3588.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s.dtsi create mode 100644 drivers/clk/rockchip/clk-rk3588.c create mode 100644 include/dt-bindings/clock/rk3588-cru.h