[v2,11/11] media: ccs-pll: Document the CCS PLL flags

Message ID	20250417065354.311617-12-sakari.ailus@linux.intel.com
State	New
Headers	show Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3A0E218851 for <linux-media@vger.kernel.org>; Thu, 17 Apr 2025 06:54:15 +0000 (UTC) Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo From: Sakari Ailus <sakari.ailus@linux.intel.com> To: linux-media@vger.kernel.org Cc: laurent.pinchart@ideasonboard.com, dongcheng.yan@intel.com Subject: [PATCH v2 11/11] media: ccs-pll: Document the CCS PLL flags Date: Thu, 17 Apr 2025 09:53:54 +0300 Message-Id: <20250417065354.311617-12-sakari.ailus@linux.intel.com> In-Reply-To: <20250417065354.311617-1-sakari.ailus@linux.intel.com> References: <20250417065354.311617-1-sakari.ailus@linux.intel.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	CCS PLL fixes and improvements \| expand [v2,00/11] CCS PLL fixes and improvements [v2,01/11] media: ccs-pll: Start OP pre-PLL multiplier search from correct value [v2,02/11] media: ccs-pll: Start VT pre-PLL multiplier search from correct value [v2,03/11] media: ccs-pll: Check for too high VT PLL multiplier in dual PLL case [v2,04/11] media: ccs-pll: Correctly the upper limit of maximum op_pre_pll_clk_div [v2,05/11] media: ccs-pll: Print a debug message on too high VT PLL OP clock [v2,06/11] media: ccs-pll: Drop LINK_DECOUPLED flag [v2,07/11] media: ccs-pll: Print missing PLL flags [v2,08/11] media: ccs-pll: Add a flag for even PLL multipliers [v2,09/11] media: ccs-pll: Better validate VT PLL branch [v2,10/11] media: ccs-pll: Print PLL calculator flags in the beginning [v2,11/11] media: ccs-pll: Document the CCS PLL flags

Message ID

20250417065354.311617-12-sakari.ailus@linux.intel.com

State

New

Headers

Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
From: Sakari Ailus <sakari.ailus@linux.intel.com>
To: linux-media@vger.kernel.org
Cc: laurent.pinchart@ideasonboard.com,
	dongcheng.yan@intel.com
Subject: [PATCH v2 11/11] media: ccs-pll: Document the CCS PLL flags
Date: Thu, 17 Apr 2025 09:53:54 +0300
Message-Id: <20250417065354.311617-12-sakari.ailus@linux.intel.com>
In-Reply-To: <20250417065354.311617-1-sakari.ailus@linux.intel.com>
References: <20250417065354.311617-1-sakari.ailus@linux.intel.com>
Precedence: bulk
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

Series

CCS PLL fixes and improvements | expand

Commit Message

Sakari Ailus April 17, 2025, 6:53 a.m. UTC

Document the CCS PLL flags with short comments. The CCS spec has more
information on them while the added documentation helps finding the
relevant information in the CCS spec.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
 drivers/media/i2c/ccs-pll.h | 27 ++++++++++++++++++++++++---
 1 file changed, 24 insertions(+), 3 deletions(-)

diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h
index e8297db45460..6e503fe2d591 100644
--- a/drivers/media/i2c/ccs-pll.h
+++ b/drivers/media/i2c/ccs-pll.h
@@ -18,19 +18,40 @@ 
 #define CCS_PLL_BUS_TYPE_CSI2_DPHY				0x00
 #define CCS_PLL_BUS_TYPE_CSI2_CPHY				0x01
 
-/* Old SMIA and implementation specific flags */
-/* op pix clock is for all lanes in total normally */
+/* Old SMIA and implementation specific flags. */
+/* OP PIX clock is for all lanes in total normally. */
 #define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE			BIT(0)
-#define CCS_PLL_FLAG_NO_OP_CLOCKS				BIT(1)
+
 /* CCS PLL flags */
+
+/* The sensor doesn't have OP clocks at all. */
+#define CCS_PLL_FLAG_NO_OP_CLOCKS				BIT(1)
+/* System speed model if this flag is unset. */
 #define CCS_PLL_FLAG_LANE_SPEED_MODEL				BIT(2)
+/* If set, the pre-PLL divider may have odd values, too. */
 #define CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER				BIT(4)
+/*
+ * If set, the OP PIX clock doesn't have to exactly match with data rate, it may
+ * be higher. See "OP Domain Formulas" in MIPI CCS 1.1 spec.
+ */
 #define CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV			BIT(5)
+/* If set, the VT domain may run faster than the OP domain. */
 #define CCS_PLL_FLAG_FIFO_DERATING				BIT(6)
+/* If set, the VT domain may run slower than the OP domain. */
 #define CCS_PLL_FLAG_FIFO_OVERRATING				BIT(7)
+/* If set, the PLL tree has two PLLs instead of one. */
 #define CCS_PLL_FLAG_DUAL_PLL					BIT(8)
+/*
+ * If set, the OP SYS clock is a dual data rate clock, transferring two bits per
+ * cycle instead of one.
+ */
 #define CCS_PLL_FLAG_OP_SYS_DDR					BIT(9)
+/*
+ * If set, the OP PIX clock is a dual data rate clock, transferring two bits per
+ * cycle instead of one.
+ */
 #define CCS_PLL_FLAG_OP_PIX_DDR					BIT(10)
+/* If set, the PLL multipliers are required to be even. */
 #define CCS_PLL_FLAG_EVEN_PLL_MULTIPLIER			BIT(11)
 
 /**

[v2,11/11] media: ccs-pll: Document the CCS PLL flags

Commit Message

Patch