[v2,09/11] media: ccs-pll: Better validate VT PLL branch

Message ID	20250417065354.311617-10-sakari.ailus@linux.intel.com
State	New
Headers	show Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 809AE2192F1 for <linux-media@vger.kernel.org>; Thu, 17 Apr 2025 06:54:16 +0000 (UTC) Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo From: Sakari Ailus <sakari.ailus@linux.intel.com> To: linux-media@vger.kernel.org Cc: laurent.pinchart@ideasonboard.com, dongcheng.yan@intel.com Subject: [PATCH v2 09/11] media: ccs-pll: Better validate VT PLL branch Date: Thu, 17 Apr 2025 09:53:52 +0300 Message-Id: <20250417065354.311617-10-sakari.ailus@linux.intel.com> In-Reply-To: <20250417065354.311617-1-sakari.ailus@linux.intel.com> References: <20250417065354.311617-1-sakari.ailus@linux.intel.com> Precedence: bulk MIME-Version: 1.0 Content-Transfer-Encoding: 8bit
Series	CCS PLL fixes and improvements \| expand [v2,00/11] CCS PLL fixes and improvements [v2,01/11] media: ccs-pll: Start OP pre-PLL multiplier search from correct value [v2,02/11] media: ccs-pll: Start VT pre-PLL multiplier search from correct value [v2,03/11] media: ccs-pll: Check for too high VT PLL multiplier in dual PLL case [v2,04/11] media: ccs-pll: Correctly the upper limit of maximum op_pre_pll_clk_div [v2,05/11] media: ccs-pll: Print a debug message on too high VT PLL OP clock [v2,06/11] media: ccs-pll: Drop LINK_DECOUPLED flag [v2,07/11] media: ccs-pll: Print missing PLL flags [v2,08/11] media: ccs-pll: Add a flag for even PLL multipliers [v2,09/11] media: ccs-pll: Better validate VT PLL branch [v2,10/11] media: ccs-pll: Print PLL calculator flags in the beginning [v2,11/11] media: ccs-pll: Document the CCS PLL flags

Message ID

20250417065354.311617-10-sakari.ailus@linux.intel.com

State

New

Headers

Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
From: Sakari Ailus <sakari.ailus@linux.intel.com>
To: linux-media@vger.kernel.org
Cc: laurent.pinchart@ideasonboard.com,
	dongcheng.yan@intel.com
Subject: [PATCH v2 09/11] media: ccs-pll: Better validate VT PLL branch
Date: Thu, 17 Apr 2025 09:53:52 +0300
Message-Id: <20250417065354.311617-10-sakari.ailus@linux.intel.com>
In-Reply-To: <20250417065354.311617-1-sakari.ailus@linux.intel.com>
References: <20250417065354.311617-1-sakari.ailus@linux.intel.com>
Precedence: bulk
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit

Series

CCS PLL fixes and improvements | expand

Commit Message

Sakari Ailus April 17, 2025, 6:53 a.m. UTC

Check that the VT PLL dividers are actually found, don't trust they always
are even though they should be.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
 drivers/media/i2c/ccs-pll.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c
index 3f8153fb4af0..fc6f8aff5fd8 100644
--- a/drivers/media/i2c/ccs-pll.c
+++ b/drivers/media/i2c/ccs-pll.c
@@ -449,7 +449,7 @@  static int ccs_pll_calculate_vt_tree(struct device *dev,
 	return -EINVAL;
 }
 
-static void
+static int
 ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
 		     const struct ccs_pll_branch_limits_bk *op_lim_bk,
 		     struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
@@ -572,6 +572,8 @@  ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
 		if (best_pix_div < SHRT_MAX >> 1)
 			break;
 	}
+	if (best_pix_div == SHRT_MAX >> 1)
+		return -EINVAL;
 
 	pll->vt_bk.sys_clk_div = DIV_ROUND_UP(vt_div, best_pix_div);
 	pll->vt_bk.pix_clk_div = best_pix_div;
@@ -584,6 +586,8 @@  ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
 out_calc_pixel_rate:
 	pll->pixel_rate_pixel_array =
 		pll->vt_bk.pix_clk_freq_hz * pll->vt_lanes;
+
+	return 0;
 }
 
 /*
@@ -863,8 +867,10 @@  int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
 		if (pll->flags & CCS_PLL_FLAG_DUAL_PLL)
 			break;
 
-		ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
-				     op_pll_bk, cphy, phy_const);
+		rval = ccs_pll_calculate_vt(dev, lim, op_lim_bk, pll, op_pll_fr,
+					    op_pll_bk, cphy, phy_const);
+		if (rval)
+			continue;
 
 		rval = check_bk_bounds(dev, lim, pll, PLL_VT);
 		if (rval)

[v2,09/11] media: ccs-pll: Better validate VT PLL branch

Commit Message

Patch