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b=owTWVPi4r7lmWWyRlPRQ+4+k47agi/ZugmxyEZdG/nfZRQTl5pboxQruAZHnGFKGx0 VCSgzxDzisiuNdFXVGmT1IYh/KM6YFZVLUmIPsNpk90c+/oXhNOxOfSSmgDtxesyB4re MrfjyECajyojoOpXvox29a+E+k42RuKVjiq+Tw8SGOHt3MO+breJuS8xg31pMAAqCDqm +Q68PnkqSxErEsNWA4gyX2V8/lgFA3t/50d0CxCNHHGlP4Uhsu67TCKPAHYMsHwrKj0P bHVXSf8zURJoLarNpeZGrUgOqS8Jv1u0oGghk+lBFGqnNZalHzvGISibzidpoESMWHo9 y+UQ== X-Forwarded-Encrypted: i=1; AJvYcCWuWuyn1VzsgaVcILq4z3yVdvJijDg0+3EsnYMSUOmULLzjE1bHswyz2N9bT0XiMIhW0M69HUhk6fI6Togn6T+a/A2BqXpcF2pQM8w= X-Gm-Message-State: AOJu0YxyiOCnYenzLJ9UO3w4hhCNhNhLbBaw32JVdf6jOqSesUuxY9hc Ll4WWrDQ3SLP+IGfCq3b0H8oSSus9WTbi1UE/f2coFGJDUpZiufXN653tEz4kRFDBDW/J5D5hPj kbXya9bJnBA== X-Google-Smtp-Source: AGHT+IFl69D5om/H+B54ETJ2PMG3nixPpLSKdXlaMOhDwBY7IXqpN0xGnNqZTl237/xQEoI2pJqnIU8A60Nk+w== X-Received: from szatan.c.googlers.com ([fda3:e722:ac3:cc00:28:9cb1:c0a8:2d83]) (user=panikiel job=sendgmr) by 2002:a05:6902:1007:b0:dd1:38ec:905d with SMTP id 3f1490d57ef6-debb9e0bdeemr176276.11.1715097329468; Tue, 07 May 2024 08:55:29 -0700 (PDT) Date: Tue, 7 May 2024 15:54:12 +0000 In-Reply-To: <20240507155413.266057-1-panikiel@google.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240507155413.266057-1-panikiel@google.com> X-Mailer: git-send-email 2.45.0.rc1.225.g2a3ae87e7f-goog Message-ID: <20240507155413.266057-10-panikiel@google.com> Subject: [PATCH v3 09/10] media: dt-bindings: Add Intel Displayport RX IP From: " =?utf-8?q?Pawe=C5=82_Anikiel?= " To: airlied@gmail.com, akpm@linux-foundation.org, conor+dt@kernel.org, daniel@ffwll.ch, dinguyen@kernel.org, hverkuil-cisco@xs4all.nl, krzysztof.kozlowski+dt@linaro.org, maarten.lankhorst@linux.intel.com, mchehab@kernel.org, mripard@kernel.org, robh+dt@kernel.org, tzimmermann@suse.de Cc: devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, chromeos-krk-upstreaming@google.com, " =?utf-8?q?Pawe=C5=82_Anikiel?= " Add dt binding for the Intel Displayport receiver FPGA IP. It is a part of the DisplayPort Intel FPGA IP Core, and supports DisplayPort 1.4, HBR3 video capture and Multi-Stream Transport. The user guide can be found here: https://www.intel.com/programmable/technical-pdfs/683273.pdf Signed-off-by: Paweł Anikiel --- .../devicetree/bindings/media/intel,dprx.yaml | 172 ++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/intel,dprx.yaml diff --git a/Documentation/devicetree/bindings/media/intel,dprx.yaml b/Documentation/devicetree/bindings/media/intel,dprx.yaml new file mode 100644 index 000000000000..01bed858f746 --- /dev/null +++ b/Documentation/devicetree/bindings/media/intel,dprx.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/intel,dprx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel DisplayPort RX IP + +maintainers: + - Paweł Anikiel + +description: | + The Intel Displayport RX IP is a part of the DisplayPort Intel FPGA IP + Core. It implements a DisplayPort 1.4 receiver capable of HBR3 video + capture and Multi-Stream Transport. + + The IP features a large number of configuration parameters, found at: + https://www.intel.com/content/www/us/en/docs/programmable/683273/23-3-20-0-1/sink-parameters.html + + The following parameters have to be enabled: + - Support DisplayPort sink + - Enable GPU control + The following parameters have to be set in the devicetree: + - RX maximum link rate (using link-frequencies) + - Maximum lane count (using data-lanes) + - Support MST (using multi-stream-support) + - Max stream count (inferred from the number of ports) + +properties: + compatible: + const: intel,dprx-20.0.1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + description: MST virtual channel 0 or SST main link + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + + properties: + link-frequencies: true + + data-lanes: + minItems: 1 + maxItems: 4 + + multi-stream-support: true + + required: + - data-lanes + - link-frequencies + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 0 or SST main link + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 1 + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 2 + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: MST virtual channel 3 + + +required: + - compatible + - reg + - interrupts + - ports + +additionalProperties: false + +examples: + - | + #include + + dp-receiver@c0062000 { + compatible = "intel,dprx-20.0.1"; + reg = <0xc0062000 0x800>; + interrupt-parent = <&dprx_mst_irq>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dprx_mst_in: endpoint { + remote-endpoint = <&dp_input_mst_0>; + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 + 5400000000 8100000000>; + multi-stream-support; + }; + }; + + port@1 { + reg = <1>; + dprx_mst_0: endpoint { + remote-endpoint = <&video_mst0_0>; + }; + }; + + port@2 { + reg = <2>; + dprx_mst_1: endpoint { + remote-endpoint = <&video_mst1_0>; + }; + }; + + port@3 { + reg = <3>; + dprx_mst_2: endpoint { + remote-endpoint = <&video_mst2_0>; + }; + }; + + port@4 { + reg = <4>; + dprx_mst_3: endpoint { + remote-endpoint = <&video_mst3_0>; + }; + }; + }; + }; + + - | + dp-receiver@c0064000 { + compatible = "intel,dprx-20.0.1"; + reg = <0xc0064000 0x800>; + interrupt-parent = <&dprx_sst_irq>; + interrupts = <0 IRQ_TYPE_EDGE_RISING>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dprx_sst_in: endpoint { + remote-endpoint = <&dp_input_sst_0>; + data-lanes = <0 1 2 3>; + link-frequencies = /bits/ 64 <1620000000 2700000000 + 5400000000 8100000000>; + }; + }; + + port@1 { + reg = <1>; + dprx_sst_0: endpoint { + remote-endpoint = <&video_sst_0>; + }; + }; + }; + };