From patchwork Sat Dec 23 18:29:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?SmFzb24tSkggTGluICjmnpfnnb/npaUp?= X-Patchwork-Id: 758734 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59F8512E55; Sat, 23 Dec 2023 18:29:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="mqWBZwEz" X-UUID: 39bb10c0a1c111eeba30773df0976c77-20231224 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Enku7WLxNyoiQmtEW8rdeh9ClXh758cvt9RXNM2nDG8=; b=mqWBZwEzRhUfVJg+ZquADwv0sVcaCYzvzEYCwqOropIt0S8IL8YH5SbbEhPIy/8fqhzP5m3c4SEIa5jV5agDTO8+ZNl6ZBqN7WueQII2jp1kYaN3bpwODg4Bq0HtqV4hHVyDlmi5nv/L5cJn80295H+DOtznKAfzlpagMO2iuZs=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.35, REQID:efbba2db-8051-46ae-9c29-3397940637bf, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5d391d7, CLOUDID:b35d7f8d-e2c0-40b0-a8fe-7c7e47299109, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 39bb10c0a1c111eeba30773df0976c77-20231224 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1727850562; Sun, 24 Dec 2023 02:29:36 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Sun, 24 Dec 2023 02:29:35 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Sun, 24 Dec 2023 02:29:34 +0800 From: Jason-JH.Lin To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Kuang Hu CC: , , , , , , , Jason-ch Chen , Johnson Wang , "Jason-JH . Lin" , Singo Chang , Nancy Lin , Shawn Sung , , Jeffrey Kardatzke Subject: [PATCH v3 06/11] drm/mediatek: Add get_sec_port interface to mtk_ddp_comp Date: Sun, 24 Dec 2023 02:29:27 +0800 Message-ID: <20231223182932.27683-7-jason-jh.lin@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231223182932.27683-1-jason-jh.lin@mediatek.com> References: <20231223182932.27683-1-jason-jh.lin@mediatek.com> Precedence: bulk X-Mailing-List: linux-media@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MTK: N Add get_sec_port interface to ddp_comp to get the secure port settings from ovl and ovl_adaptor. Then mediatek-drm will use secure cmdq driver to configure DRAM access permission in secure world by their secure port settings. Signed-off-by: Jason-JH.Lin --- drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index b5a05ca3a385..1e6a120a103d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -84,6 +84,7 @@ struct mtk_ddp_comp_funcs { void (*add)(struct device *dev, struct mtk_mutex *mutex); void (*remove)(struct device *dev, struct mtk_mutex *mutex); unsigned int (*encoder_index)(struct device *dev); + u64 (*get_sec_port)(struct mtk_ddp_comp *comp, unsigned int idx); }; struct mtk_ddp_comp { @@ -199,6 +200,14 @@ static inline unsigned int mtk_ddp_gamma_get_lut_size(struct mtk_ddp_comp *comp) return 0; } +static inline u64 mtk_ddp_comp_layer_get_sec_port(struct mtk_ddp_comp *comp, + unsigned int idx) +{ + if (comp->funcs && comp->funcs->get_sec_port) + return comp->funcs->get_sec_port(comp, idx); + return 0; +} + static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state) {