| Message ID | 20230922072116.11009-10-moudy.ho@mediatek.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | introduce more MDP3 components in MT8195 | expand |
On Fri, Sep 22, 2023 at 03:21:09PM +0800, Moudy Ho wrote: > Add the fundamental hardware configuration of component STITCH, STITCH? You mean TCC? > which is controlled by MDP3 on MT8195. > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > --- > .../bindings/media/mediatek,mdp3-tcc.yaml | 60 +++++++++++++++++++ > 1 file changed, 60 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml > new file mode 100644 > index 000000000000..245e2134c74a > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml > @@ -0,0 +1,60 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Media Data Path 3 TCC > + > +maintainers: > + - Matthias Brugger <matthias.bgg@gmail.com> > + > +description: > + One of Media Data Path 3 (MDP3) components used to support > + HDR gamma curve conversion HDR displays. Please say what the block does. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8195-mdp3-tcc > + > + reg: > + maxItems: 1 > + > + mediatek,gce-client-reg: > + description: > + The register of display function block to be set by gce. There are 4 arguments, > + such as gce node, subsys id, offset and register size. The subsys id that is > + mapping to the register of display function blocks is defined in the gce header > + include/dt-bindings/gce/<chip>-gce.h of each chips. > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + items: > + - description: phandle of GCE > + - description: GCE subsys id > + - description: register offset > + - description: register size > + maxItems: 1 > + > + clocks: > + minItems: 1 > + > +required: > + - compatible > + - reg > + - mediatek,gce-client-reg > + - clocks > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt8195-clk.h> > + #include <dt-bindings/gce/mt8195-gce.h> > + > + display@1400b000 { > + compatible = "mediatek,mt8195-mdp3-tcc"; > + reg = <0x1400b000 0x1000>; > + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; > + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; > + }; > -- > 2.18.0 >
On Mon, 2023-09-25 at 11:09 -0500, Rob Herring wrote: > > External email : Please do not click links or open attachments until > you have verified the sender or the content. > On Fri, Sep 22, 2023 at 03:21:09PM +0800, Moudy Ho wrote: > > Add the fundamental hardware configuration of component STITCH, > > STITCH? You mean TCC? > Hi Rob, Apologize for the typo, it will be promptly addressed and corrected. > > which is controlled by MDP3 on MT8195. > > > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > > --- > > .../bindings/media/mediatek,mdp3-tcc.yaml | 60 > +++++++++++++++++++ > > 1 file changed, 60 insertions(+) > > create mode 100644 > Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml > > > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3- > tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3- > tcc.yaml > > new file mode 100644 > > index 000000000000..245e2134c74a > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3- > tcc.yaml > > @@ -0,0 +1,60 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: MediaTek Media Data Path 3 TCC > > + > > +maintainers: > > + - Matthias Brugger <matthias.bgg@gmail.com> > > + > > +description: > > + One of Media Data Path 3 (MDP3) components used to support > > + HDR gamma curve conversion HDR displays. > > Please say what the block does. > I will provide a more specific description for this. Sincerely, Moudy > > + > > +properties: > > + compatible: > > + enum: > > + - mediatek,mt8195-mdp3-tcc > > + > > + reg: > > + maxItems: 1 > > + > > + mediatek,gce-client-reg: > > + description: > > + The register of display function block to be set by gce. > There are 4 arguments, > > + such as gce node, subsys id, offset and register size. The > subsys id that is > > + mapping to the register of display function blocks is > defined in the gce header > > + include/dt-bindings/gce/<chip>-gce.h of each chips. > > + $ref: /schemas/types.yaml#/definitions/phandle-array > > + items: > > + items: > > + - description: phandle of GCE > > + - description: GCE subsys id > > + - description: register offset > > + - description: register size > > + maxItems: 1 > > + > > + clocks: > > + minItems: 1 > > + > > +required: > > + - compatible > > + - reg > > + - mediatek,gce-client-reg > > + - clocks > > + > > +additionalProperties: false > > + > > +examples: > > + - | > > + #include <dt-bindings/clock/mt8195-clk.h> > > + #include <dt-bindings/gce/mt8195-gce.h> > > + > > + display@1400b000 { > > + compatible = "mediatek,mt8195-mdp3-tcc"; > > + reg = <0x1400b000 0x1000>; > > + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 > 0x1000>; > > + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; > > + }; > > -- > > 2.18.0 > >
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml new file mode 100644 index 000000000000..245e2134c74a --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 TCC + +maintainers: + - Matthias Brugger <matthias.bgg@gmail.com> + +description: + One of Media Data Path 3 (MDP3) components used to support + HDR gamma curve conversion HDR displays. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-tcc + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/<chip>-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + minItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8195-clk.h> + #include <dt-bindings/gce/mt8195-gce.h> + + display@1400b000 { + compatible = "mediatek,mt8195-mdp3-tcc"; + reg = <0x1400b000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; + };
Add the fundamental hardware configuration of component STITCH, which is controlled by MDP3 on MT8195. Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> --- .../bindings/media/mediatek,mdp3-tcc.yaml | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml