From patchwork Fri Dec 16 13:44:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jai Luthra X-Patchwork-Id: 635051 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 606E8C4332F for ; Fri, 16 Dec 2022 13:44:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230182AbiLPNoh (ORCPT ); Fri, 16 Dec 2022 08:44:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229627AbiLPNog (ORCPT ); Fri, 16 Dec 2022 08:44:36 -0500 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CEF4D20BED for ; Fri, 16 Dec 2022 05:44:35 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2BGDiOcK053104; Fri, 16 Dec 2022 07:44:24 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1671198264; bh=vzPCuBm79L53NueQA0TtEVEFhfkN6Jmg2gif13XrwI4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fzOX/nRsPs4h+2KZPUzx1PjdIwQy0qBiYRqEHrBvE9IFxLbh1Lm3Z8tfVhlRP0cJa I0SyWhO6dTWFa3Tbv3ExHPtyxeyS6oupRXmxX6lT9YiZn2RlorohediUmDnupAmiCz gX8SPm7KA5xYrVvu0Ec04MqSnYPomi67WrB2yM78= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2BGDiNX6094380 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 16 Dec 2022 07:44:23 -0600 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 16 Dec 2022 07:44:23 -0600 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 16 Dec 2022 07:44:23 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2BGDiMH9071223; Fri, 16 Dec 2022 07:44:23 -0600 From: Jai Luthra To: Steve Longerbeam , Mauro Carvalho Chehab , Sakari Ailus CC: , Nishanth Menon Subject: [PATCH 2/3] media: ov5640: Honor RESETB to SMBUS time t4 in init_setting Date: Fri, 16 Dec 2022 19:14:08 +0530 Message-ID: <20221216134409.6868-3-j-luthra@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221216134409.6868-1-j-luthra@ti.com> References: <20221216134409.6868-1-j-luthra@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Nishanth Menon OV5640 Datasheet[1] Figures 2-3 and 2-4 indicate the timing sequences that is expected during various initialization steps. Note the t4 >= 20ms, delay from RESETB pull high to SCCB initialization As indicated in section 2.8, the RESETB assertion can either be via external pin control OR via the register 0x3008 bit 7. The initialization sequence asserts bit7, but on deassert, we do not wait for the reset delay. [1] https://cdn.sparkfun.com/datasheets/Sensors/LightImaging/OV5640_datasheet.pdf Fixes: 19a81c1426c1 ("[media] add Omnivision OV5640 sensor driver") Signed-off-by: Nishanth Menon --- drivers/media/i2c/ov5640.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c index 4bb7bf557cfa..fa84e60de0db 100644 --- a/drivers/media/i2c/ov5640.c +++ b/drivers/media/i2c/ov5640.c @@ -532,7 +532,7 @@ static const struct v4l2_mbus_framefmt ov5640_default_fmt = { }; static const struct reg_value ov5640_init_setting[] = { - {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 5}, {0x3008, 0x42, 0, 0}, + {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 5}, {0x3008, 0x42, 0, 20}, {0x3103, 0x03, 0, 0}, {0x3630, 0x36, 0, 0}, {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0}, {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0},