From patchwork Mon Apr 11 07:49:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 559829 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F0C9C433F5 for ; Mon, 11 Apr 2022 07:49:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245676AbiDKHv5 (ORCPT ); Mon, 11 Apr 2022 03:51:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60734 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S245669AbiDKHvw (ORCPT ); Mon, 11 Apr 2022 03:51:52 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5639125C55; Mon, 11 Apr 2022 00:49:39 -0700 (PDT) X-UUID: c4f34ba61b6e428da01c488d33160f17-20220411 X-UUID: c4f34ba61b6e428da01c488d33160f17-20220411 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 56403225; Mon, 11 Apr 2022 15:49:30 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 11 Apr 2022 15:49:27 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 11 Apr 2022 15:49:27 +0800 From: Moudy Ho To: Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Hans Verkuil CC: Chun-Kuang Hu , Rob Landley , Laurent Pinchart , , , , , , Alexandre Courbot , , , , , Benjamin Gaignard , AngeloGioacchino Del Regno , "daoyuan huang" , Ping-Hsun Wu , , , , , , , , , Subject: [PATCH v15 4/6] dt-bindings: soc: mediatek: add gce-client-reg for MUTEX Date: Mon, 11 Apr 2022 15:49:23 +0800 Message-ID: <20220411074925.25539-5-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220411074925.25539-1-moudy.ho@mediatek.com> References: <20220411074925.25539-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org In order to allow modules with latency requirements such as MDP3 to set registers through CMDQ, add the relevant GCE property. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu Reviewed-by: Rob Herring --- .../bindings/soc/mediatek/mediatek,mutex.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index 40598243c84d..e4399e1f9b1c 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -60,6 +60,18 @@ properties: include/dt-bindings/gce/-gce.h of each chips. $ref: /schemas/types.yaml#/definitions/uint32-array + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + description: The register of client driver can be configured by gce with + 4 arguments defined in this property. Each GCE subsys id is mapping to + a client defined in the header include/dt-bindings/gce/-gce.h. + required: - compatible - reg