From patchwork Thu Mar 3 15:36:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 547989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87A30C433FE for ; Thu, 3 Mar 2022 15:38:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234573AbiCCPjX (ORCPT ); Thu, 3 Mar 2022 10:39:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234598AbiCCPjU (ORCPT ); Thu, 3 Mar 2022 10:39:20 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A2BF148665; Thu, 3 Mar 2022 07:38:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1646321914; x=1677857914; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LPz0O/j6T/R5IOZ/0HdGMFHbVlsAXUy78/qaH+crieA=; b=gA4N/WW8OxRXLxUVzal/+QOdxXC8vLi3LznAeYJWCaSbZdE7bMxrg6pA VM8NfC2jQVDIkyBHfAc4v0pvPgn8484muWeBUMDGdbcILpiAba6sQ5OOm xkHdprrOw8Xvznt0TXnxiM/pXX6xIEzxDlWyMb66Z/iblb9G/CR+17q3Q KMOhND59aRwo+9j42fQPT0H6tIgoMZF/T6mWgzaydAWR6vN+fczJFrHB/ AO77BBOxYhbqqfak7wswZS6IuzSXnhFkPz87SY92frAWBGcvYDEF5FZG/ mQKfCD5r43BsZctSAvvpO/3IUSIBaNeO/7NXB0lwvdGfySg9ZBEeyTc6O A==; X-IronPort-AV: E=Sophos;i="5.90,151,1643698800"; d="scan'208";a="87706079" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 03 Mar 2022 08:38:28 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 3 Mar 2022 08:38:26 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 3 Mar 2022 08:38:18 -0700 From: Eugen Hristev To: , CC: , , , , , , Eugen Hristev Subject: [PATCH v6 11/13] ARM: dts: at91: sama7g5: add nodes for video capture Date: Thu, 3 Mar 2022 17:36:16 +0200 Message-ID: <20220303153618.2084156-12-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303153618.2084156-1-eugen.hristev@microchip.com> References: <20220303153618.2084156-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add node for the XISC (eXtended Image Sensor Controller) and CSI2DC (csi2 demux controller). These nodes represent the top level of the video capture hardware pipeline and are directly connected in hardware. Signed-off-by: Eugen Hristev --- arch/arm/boot/dts/sama7g5.dtsi | 49 ++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index eddcfbf4d223..de43f854ce47 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -266,6 +266,55 @@ sdmmc2: mmc@e120c000 { status = "disabled"; }; + csi2dc: csi2dc@e1404000 { + compatible = "microchip,sama7g5-csi2dc"; + reg = <0xe1404000 0x500>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; + clock-names = "pclk", "scck"; + assigned-clocks = <&xisc>; + assigned-clock-rates = <266000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csi2dc_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + csi2dc_out: endpoint { + bus-width = <14>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&xisc_in>; + }; + }; + }; + }; + + xisc: xisc@e1408000 { + compatible = "microchip,sama7g5-isc"; + reg = <0xe1408000 0x2000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names = "hclock"; + #clock-cells = <0>; + clock-output-names = "isc-mck"; + + port { + xisc_in: endpoint { + bus-type = <5>; /* Parallel */ + bus-width = <14>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&csi2dc_out>; + }; + }; + }; + pwm: pwm@e1604000 { compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; reg = <0xe1604000 0x4000>;