From patchwork Thu Feb 17 13:56:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugen Hristev X-Patchwork-Id: 543551 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 902E3C433EF for ; Thu, 17 Feb 2022 14:00:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241609AbiBQOBM (ORCPT ); Thu, 17 Feb 2022 09:01:12 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:37862 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241598AbiBQOBL (ORCPT ); Thu, 17 Feb 2022 09:01:11 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5CB72B04A8; Thu, 17 Feb 2022 06:00:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1645106455; x=1676642455; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LPz0O/j6T/R5IOZ/0HdGMFHbVlsAXUy78/qaH+crieA=; b=mqyyiGgomU+PlYV9YKmeK7FEU8LKAp4x0JKW/VAH9yjd8F7axzJu42FD HqteaUtFIqW2K/4uI6FdH1Fcj3bSqdcwAYNufD+3oygo3btoP1Gpd4GQv 47LcSTS9sP3zfP0R+lCK9tiF6ln3lTr/Mz2I9lq1LJjwtS16quLmb2Nho uUUm0aRcjpBz+BpoIbStbjkxeEL8aE4b/z91uU81CLmW3U0bPgF2tbYoY yNksN6MGI913W10XYw5v/5knmMDaCZ4dnizVkmFHL/pONQQDjkJ1rrjFG h9pWLr8ae3R7R4JRBc/VK7+2VGWkChvzuCwsDMeNAEcittPKvbqbNk6NS A==; IronPort-SDR: TRRtxLkLtlDP3IVsRHBycrDjE1LpoybqYFtoZZrDp1FB7ZnRml3jC/9wEepgEjwPPmHLFsSlIh WRsgq6Sn4JRdAtLOoDpUhhB61ZzXG5PbcgJazDBQfMzMU30HTKN7w0dE0254KKH8dbSWaUWH/U sJ7pz3Pq4YdjQXVT2UE7azVWSAr8UgOH4CalSbyfMCuIzhEKFiBsXumeK1UlaHpD/hePDXMP6Q 42D/cezJHqcU2+SRavBLkIvOydMluFiNPyI3z0m5PNo00l6LQzsvFkU9JkUumz7Nv2PsiN8dAz uPgOBSvriUVaGeRIG69id1V2 X-IronPort-AV: E=Sophos;i="5.88,376,1635231600"; d="scan'208";a="162632307" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Feb 2022 07:00:55 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Thu, 17 Feb 2022 07:00:55 -0700 Received: from ROB-ULT-M18282.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Thu, 17 Feb 2022 07:00:41 -0700 From: Eugen Hristev To: , , , CC: , , , , "Eugen Hristev" Subject: [PATCH v5 11/13] ARM: dts: at91: sama7g5: add nodes for video capture Date: Thu, 17 Feb 2022 15:56:43 +0200 Message-ID: <20220217135645.1427466-12-eugen.hristev@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220217135645.1427466-1-eugen.hristev@microchip.com> References: <20220217135645.1427466-1-eugen.hristev@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add node for the XISC (eXtended Image Sensor Controller) and CSI2DC (csi2 demux controller). These nodes represent the top level of the video capture hardware pipeline and are directly connected in hardware. Signed-off-by: Eugen Hristev --- arch/arm/boot/dts/sama7g5.dtsi | 49 ++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index eddcfbf4d223..de43f854ce47 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -266,6 +266,55 @@ sdmmc2: mmc@e120c000 { status = "disabled"; }; + csi2dc: csi2dc@e1404000 { + compatible = "microchip,sama7g5-csi2dc"; + reg = <0xe1404000 0x500>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; + clock-names = "pclk", "scck"; + assigned-clocks = <&xisc>; + assigned-clock-rates = <266000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csi2dc_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + csi2dc_out: endpoint { + bus-width = <14>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&xisc_in>; + }; + }; + }; + }; + + xisc: xisc@e1408000 { + compatible = "microchip,sama7g5-isc"; + reg = <0xe1408000 0x2000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names = "hclock"; + #clock-cells = <0>; + clock-output-names = "isc-mck"; + + port { + xisc_in: endpoint { + bus-type = <5>; /* Parallel */ + bus-width = <14>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&csi2dc_out>; + }; + }; + }; + pwm: pwm@e1604000 { compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; reg = <0xe1604000 0x4000>;