From patchwork Tue Jan 11 16:16:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dafna Hirschfeld X-Patchwork-Id: 531897 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BAE74C43219 for ; Tue, 11 Jan 2022 16:16:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349911AbiAKQQi (ORCPT ); Tue, 11 Jan 2022 11:16:38 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349908AbiAKQQa (ORCPT ); Tue, 11 Jan 2022 11:16:30 -0500 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64BE7C061757; Tue, 11 Jan 2022 08:16:29 -0800 (PST) Received: from localhost.localdomain (unknown [IPv6:2a00:c281:14a3:8100:5418:23c4:e539:4c3e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: dafna) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id 55E511F43AA8; Tue, 11 Jan 2022 16:16:26 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1641917787; bh=z4yjDZMHbL7khpV9qKXUGvaNdJTMLt5a7ZsWb+Iwb9w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B5FzCJgq7lwrjSTt9MA4ENfc+D4XThWM0hGCUWF8Zy4OW5UMt+75P0SQWnMspKxu0 ifhoCcFkMKd1LiDiYKCC7X2WYIqk3CbECnNEr1lwdIC5/ChxH0WYAYVLASMh1WyrJY HmWtzLM6tr5Xrd5uqYr+Wc9Xr9agKaJc/HsZT5SPjYpyERSsiUbYI9SFYhWHg6JVRj 3JyhEbROHfzA/HiavYbPocuCB1GcIsdA0S2q0XB50kBSNh9mWnqmTZN1GClPCZePnc GO42d4i0BOFS89EVZT1hDoLUfgZ/ZNoYkNaiqSz4c3T0i5/Ks9n7MhpnwfNTcwb77g 08/wZErNHXmFw== From: Dafna Hirschfeld To: linux-media@vger.kernel.org Cc: Dafna Hirschfeld , Robert Beckett , Mauro Carvalho Chehab , Greg Kroah-Hartman , linux-staging@lists.linux.dev (open list:STAGING SUBSYSTEM), linux-kernel@vger.kernel.org (open list), laurent.pinchart@ideasonboard.com, hverkuil@xs4all.nl, kernel@collabora.com, dafna3@gmail.com, kiril.bicevski@collabora.com, Nas Chung , lafley.kim@chipsnmedia.com, scott.woo@chipsnmedia.com, olivier.crete@collabora.com, dan.carpenter@oracle.com, rdunlap@infradead.org, daniel@0x0f.com Subject: [PATCH v5 4/6] staging: media: wave5: Add TODO file Date: Tue, 11 Jan 2022 18:16:02 +0200 Message-Id: <20220111161604.22579-5-dafna.hirschfeld@collabora.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220111161604.22579-1-dafna.hirschfeld@collabora.com> References: <20220111161604.22579-1-dafna.hirschfeld@collabora.com> Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add a TODO file listing all that is need for destaging. Signed-off-by: Robert Beckett Signed-off-by: Dafna Hirschfeld --- drivers/staging/media/wave5/TODO | 64 ++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) create mode 100644 drivers/staging/media/wave5/TODO diff --git a/drivers/staging/media/wave5/TODO b/drivers/staging/media/wave5/TODO new file mode 100644 index 000000000000..425ed42a234c --- /dev/null +++ b/drivers/staging/media/wave5/TODO @@ -0,0 +1,64 @@ +* Test on real silicon once available + + This driver has so far been tested on pre-silicon FPGA and on the beta BeagleV + board which uses the StarFive JH7100 beta SoC. + + Testing on FPGA shows it working fine, though the FPGA uses polled interrupts + and copied buffers between the host and it's on board RAM. + + Testing on BeagleV shows buffer corruption that is currently attributed to a + known silicon issue in the SoC that makes the cache coherent interconnect not + so coherent. + This can likely be solved when the riscv non-coherent dma support lands and + provide optional v4l2 non-contiguous allocator, though it remains to be seen + whether support non-coherent use cases will be useful in real world hw. + + Until we can test and resolve any issues on final silicon (due 2H 2021) + this driver should remain in staging. + +* Handle interrupts better + + Currently the interrupt handling uses an unusual design employing a kfifo to + transfer irq status to irq thread. This was done as a work around for dropped + interrupts seen with IRQF_ONESHOT based handling. + + This needs further investigation and fixing properly, with the aid of + C&M and StarFive engineers. + +* Fix early end of stream handling + + When using a gstreamer pipeline like this: + gst-launch-1.0 filesrc location= ! parsebin ! h264parse ! v4l2h264dec ! jpegenc ! identity eos-after=3 ! multifilesink location=%05d.jpeg + i.e. forced eos after 3 buffers + the pipeline stalls on exit waiting for end of job. + We need to add some form of early exit detection, instead of the current + behaviour of only considering a job finish on PIC_END. + +* Support more formats + + The current frontend v4l2 layer only supports V4L2_PIX_FMT_HEVC and + V4L2_PIX_FMT_H264. + The backend logic supports other formats, so we should wire up the support + for further bitsream formats. + +* appropreate error handling: +allocation failure, mutex acquire failure etc. + +* remove all unused struct fields + +* change struct fields to 'bool' type or bitfield when appropreate +Likely good candidates are fields named '*_enable' , '*_on' + +* handle vdi_allocate_dma_memory failure , each function has to clean after itself + +* make sure that 'u32', 's32' etc. are only used when reading/writing hw +and change s32 to u32 when s32 is not required + +* power management handling - add (runtime_)suspen/resume cb where the clock is enabled + +* fix checkpatch issues (mostly fixes , only left to fix MACRO_ARG_REUSE, LONG_LINE) + +* revise logic of wave5_vpu_(dec/enc)_register_framebuffer + +* check if the normal kernel endianness/__swab32 routines are sufficient. (instead of the ones + implemented in the driver