From patchwork Fri Jul 2 09:59:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 469683 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER, INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4D40C11F6A for ; Fri, 2 Jul 2021 09:59:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CF919613CD for ; Fri, 2 Jul 2021 09:59:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231708AbhGBKB7 (ORCPT ); Fri, 2 Jul 2021 06:01:59 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:55538 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231563AbhGBKB5 (ORCPT ); Fri, 2 Jul 2021 06:01:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1625219963; x=1627811963; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=i21HcJrDIPePWdeQLseYqFtUzqXx/iuUIf/ULTnFwYs=; b=si0v7WOeT9qi8hhpBwz0KCjcfphlAEFjXftqE5V59Ouoh4Mp0qblg9X+u0i7e3rd Vg40tPQ+BTD2ccTsy9ntK46Lw3ucQkIwxKFaFct5GGNl5Gh4nW6Ikb7czXXx5piE 3QEmsR7AV9bdPeTk9Il2riX9ripe3lIKZh3ZzZVK6Nk=; X-AuditID: c39127d2-a9fbd70000001c5e-76-60dee37bbdba Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 54.01.07262.B73EED06; Fri, 2 Jul 2021 11:59:23 +0200 (CEST) Received: from lws-riedmueller.phytec.de ([172.16.23.108]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021070211592312-1081047 ; Fri, 2 Jul 2021 11:59:23 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Rob Herring Cc: Mauro Carvalho Chehab , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Christian Hemp , Stefan Riedmueller Subject: [PATCH v3 2/6] media: mt9p031: Make pixel clock polarity configurable by DT Date: Fri, 2 Jul 2021 11:59:18 +0200 Message-Id: <20210702095922.118614-3-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210702095922.118614-1-s.riedmueller@phytec.de> References: <20210702095922.118614-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 02.07.2021 11:59:23, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 02.07.2021 11:59:23 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFLMWRmVeSWpSXmKPExsWyRoCBS7f68b0EgwX/1SzmHznHatE5cQm7 xeVdc9gsejZsZbVYtukPk0Xr3iPsFp+2fGNyYPeY3TGT1WPTqk42j3knAz0+b5ILYInisklJ zcksSy3St0vgyljb2cBesEmqYsLiaywNjOvEuhg5OSQETCTmbHnA2MXIxSEksI1R4tbpu1DO NUaJ7/+2M4FUsQkYSSyY1ghmiwhESfw838MCUsQs0MwksWn5NDaQhLBAiMTVvm1gNouAisTl J/eAGjg4eAVsJdr3ckJsk5eYeek7O4jNKWAncebmURYQWwio5Gj/L1YQm1dAUOLkzCdg8yUE rjBKzLi0jAmiWUji9OKzzCA2s4C2xLKFr5knMArMQtIzC0lqASPTKkah3Mzk7NSizGy9gozK ktRkvZTUTYzA8D08Uf3SDsa+OR6HGJk4GA8xSnAwK4nwhs67lyDEm5JYWZValB9fVJqTWnyI UZqDRUmcdwNvSZiQQHpiSWp2ampBahFMlomDU6qBMWRDV27Y/HcJl4yv9HzPDNh+d01gRxFj fIrxl6d3thd1lZjzLFdZu5XR/L9BSIqvW9tRnZ0nordWdtvufie5fN7GxltpqypVAl3muWhJ 2Jc26qXntb3JlZgw2+WX92GFxicbBNqPZG6of5ma4qjUM2v2uVXZbhMfPtrC0Rf2zNsoeFPJ Bol7SizFGYmGWsxFxYkASClN8U0CAAA= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Christian Hemp Evaluate the desired pixel clock polarity from the device tree. Signed-off-by: Christian Hemp Signed-off-by: Stefan Riedmueller --- drivers/media/i2c/Kconfig | 1 + drivers/media/i2c/mt9p031.c | 20 +++++++++++++++++++- include/media/i2c/mt9p031.h | 1 + 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 588f8eb95984..1f9e98be8066 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -1187,6 +1187,7 @@ config VIDEO_MT9P031 select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select VIDEO_APTINA_PLL + select V4L2_FWNODE help This is a Video4Linux2 sensor driver for the Aptina (Micron) mt9p031 5 Mpixel camera. diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index 3eaaa8d44523..6a6f16df3f4a 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include "aptina-pll.h" @@ -398,6 +399,14 @@ static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on) return ret; } + /* Configure the pixel clock polarity */ + if (mt9p031->pdata && mt9p031->pdata->pixclk_pol) { + ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL, + MT9P031_PIXEL_CLOCK_INVERT); + if (ret < 0) + return ret; + } + return v4l2_ctrl_handler_setup(&mt9p031->ctrls); } @@ -1040,8 +1049,11 @@ static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = { static struct mt9p031_platform_data * mt9p031_get_pdata(struct i2c_client *client) { - struct mt9p031_platform_data *pdata; + struct mt9p031_platform_data *pdata = NULL; struct device_node *np; + struct v4l2_fwnode_endpoint endpoint = { + .bus_type = V4L2_MBUS_PARALLEL + }; if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) return client->dev.platform_data; @@ -1050,6 +1062,9 @@ mt9p031_get_pdata(struct i2c_client *client) if (!np) return NULL; + if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0) + goto done; + pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) goto done; @@ -1057,6 +1072,9 @@ mt9p031_get_pdata(struct i2c_client *client) of_property_read_u32(np, "input-clock-frequency", &pdata->ext_freq); of_property_read_u32(np, "pixel-clock-frequency", &pdata->target_freq); + pdata->pixclk_pol = !!(endpoint.bus.parallel.flags & + V4L2_MBUS_PCLK_SAMPLE_RISING); + done: of_node_put(np); return pdata; diff --git a/include/media/i2c/mt9p031.h b/include/media/i2c/mt9p031.h index 7c29c53aa988..f933cd0be8e5 100644 --- a/include/media/i2c/mt9p031.h +++ b/include/media/i2c/mt9p031.h @@ -10,6 +10,7 @@ struct v4l2_subdev; * @target_freq: Pixel clock frequency */ struct mt9p031_platform_data { + unsigned int pixclk_pol:1; int ext_freq; int target_freq; };