From patchwork Wed Dec 2 18:06:26 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 336310 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 083C1C71155 for ; Wed, 2 Dec 2020 18:12:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A3558206D5 for ; Wed, 2 Dec 2020 18:12:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2387790AbgLBSMu (ORCPT ); Wed, 2 Dec 2020 13:12:50 -0500 Received: from retiisi.eu ([95.216.213.190]:33498 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729033AbgLBSMt (ORCPT ); Wed, 2 Dec 2020 13:12:49 -0500 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id AF8D7634CBE; Wed, 2 Dec 2020 20:08:32 +0200 (EET) From: Sakari Ailus To: linux-media@vger.kernel.org Cc: mchehab@kernel.org Subject: [PATCH 23/38] ccs-pll: Add C-PHY support Date: Wed, 2 Dec 2020 20:06:26 +0200 Message-Id: <20201202180641.17401-24-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201202180641.17401-1-sakari.ailus@linux.intel.com> References: <20201202180641.17401-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add C-PHY support for the CCS PLL calculator. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.c | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.c b/drivers/media/i2c/ccs-pll.c index 420d2c4d7b2c..0fa7c6f67195 100644 --- a/drivers/media/i2c/ccs-pll.c +++ b/drivers/media/i2c/ccs-pll.c @@ -145,6 +145,10 @@ static int check_all_bounds(struct device *dev, return rval; } +#define CPHY_CONST 7 +#define DPHY_CONST 16 +#define PHY_CONST_DIV 16 + /* * Heuristically guess the PLL tree for a given common multiplier and * divisor. Begin with the operational timing and continue to video @@ -162,7 +166,7 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, const struct ccs_pll_branch_limits_bk *op_lim_bk, struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr, struct ccs_pll_branch_bk *op_pll_bk, uint32_t mul, - uint32_t div, uint32_t l) + uint32_t div, uint32_t l, bool cphy, uint32_t phy_const) { uint32_t sys_div; uint32_t best_pix_div = INT_MAX >> 1; @@ -254,9 +258,11 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, if (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL) op_pll_bk->pix_clk_div = pll->bits_per_pixel - * pll->op_lanes / pll->csi2.lanes / l; + * pll->op_lanes * phy_const + / PHY_CONST_DIV / pll->csi2.lanes / l; else - op_pll_bk->pix_clk_div = pll->bits_per_pixel / l; + op_pll_bk->pix_clk_div = + pll->bits_per_pixel * phy_const / PHY_CONST_DIV / l; op_pll_bk->pix_clk_freq_hz = op_pll_bk->sys_clk_freq_hz / op_pll_bk->pix_clk_div; @@ -295,10 +301,11 @@ __ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, */ dev_dbg(dev, "scale_m: %u\n", pll->scale_m); min_vt_div = DIV_ROUND_UP(pll->bits_per_pixel * op_pll_bk->sys_clk_div - * pll->scale_n * pll->vt_lanes, + * pll->scale_n * pll->vt_lanes * phy_const, (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? pll->csi2.lanes : 1) - * vt_op_binning_div * pll->scale_m); + * vt_op_binning_div * pll->scale_m + * PHY_CONST_DIV); /* Find smallest and biggest allowed vt divisor. */ dev_dbg(dev, "min_vt_div: %u\n", min_vt_div); @@ -408,6 +415,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, const struct ccs_pll_branch_limits_bk *op_lim_bk = &lim->op_bk; struct ccs_pll_branch_fr *op_pll_fr = &pll->vt_fr; struct ccs_pll_branch_bk *op_pll_bk = &pll->op_bk; + bool cphy = pll->bus_type == CCS_PLL_BUS_TYPE_CSI2_CPHY; + uint32_t phy_const = cphy ? CPHY_CONST : DPHY_CONST; uint16_t min_op_pre_pll_clk_div; uint16_t max_op_pre_pll_clk_div; uint32_t mul, div; @@ -465,14 +474,21 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? 1 : pll->csi2.lanes); break; + case CCS_PLL_BUS_TYPE_CSI2_CPHY: + op_pll_bk->sys_clk_freq_hz = + pll->link_freq + * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? + 1 : pll->csi2.lanes); + break; default: return -EINVAL; } pll->pixel_rate_csi = - op_pll_bk->sys_clk_freq_hz - * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? - pll->csi2.lanes : 1) / pll->bits_per_pixel / l; + div_u64((uint64_t)op_pll_bk->sys_clk_freq_hz + * (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ? + pll->csi2.lanes : 1) * PHY_CONST_DIV, + phy_const * pll->bits_per_pixel * l); /* Figure out limits for OP pre-pll divider based on extclk */ dev_dbg(dev, "min / max op_pre_pll_clk_div: %u / %u\n", @@ -510,7 +526,8 @@ int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim, (pll->flags & CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER) ? 1 : 2 - (op_pll_fr->pre_pll_clk_div & 1)) { rval = __ccs_pll_calculate(dev, lim, op_lim_fr, op_lim_bk, pll, - op_pll_fr, op_pll_bk, mul, div, l); + op_pll_fr, op_pll_bk, mul, div, l, + cphy, phy_const); if (rval) continue;