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[109.252.192.83]) by smtp.gmail.com with ESMTPSA id m6sm640725ljc.112.2020.11.04.15.45.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Nov 2020 15:45:01 -0800 (PST) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Alan Stern , Peter Chen , Mark Brown , Liam Girdwood , Adrian Hunter , Krzysztof Kozlowski , Greg Kroah-Hartman , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Ulf Hansson , Mauro Carvalho Chehab , Rob Herring , Marek Szyprowski , Peter Geis , Nicolas Chauvet Cc: linux-samsung-soc@vger.kernel.org, devel@driverdev.osuosl.org, linux-usb@vger.kernel.org, linux-pwm@vger.kernel.org, linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH v1 04/30] media: dt: bindings: tegra-vde: Document OPP and voltage regulator properties Date: Thu, 5 Nov 2020 02:44:01 +0300 Message-Id: <20201104234427.26477-5-digetx@gmail.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20201104234427.26477-1-digetx@gmail.com> References: <20201104234427.26477-1-digetx@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Document new DVFS OPP table and voltage regulator properties of the video decoder engine. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring --- .../devicetree/bindings/media/nvidia,tegra-vde.txt | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt index 602169b8aa19..9854fa9d3cd3 100644 --- a/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt +++ b/Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt @@ -36,6 +36,16 @@ Optional properties: - reset-names : Must include the following entries: - mc - iommus: Must contain phandle to the IOMMU device node. +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- core-supply: Phandle to voltage regulator of the SoC "core" power domain. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: One bitfield indicating: + On Tegra20: SoC process ID mask + On Tegra30+: SoC speedo ID mask + + A bitwise AND is performed against the value and if any bit + matches, the OPP gets enabled. Example: @@ -61,4 +71,6 @@ video-codec@6001a000 { reset-names = "vde", "mc"; resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; iommus = <&mc TEGRA_SWGROUP_VDE>; + operating-points-v2 = <&dvfs_opp_table>; + core-supply = <&vdd_core>; };