From patchwork Fri Sep 25 07:50:28 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 255622 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E816C4363D for ; Fri, 25 Sep 2020 08:06:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id B1FAC2085B for ; Fri, 25 Sep 2020 08:06:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=temperror (0-bit key) header.d=phytec.de header.i=@phytec.de header.b="G5HqRrJm" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727463AbgIYIGD (ORCPT ); Fri, 25 Sep 2020 04:06:03 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:61920 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727135AbgIYIF5 (ORCPT ); Fri, 25 Sep 2020 04:05:57 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a1; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1601020247; x=1603612247; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=m09GuPxODIBi6CsANbjfMfr/YvqAFgMfC3Wj/NunD5c=; b=G5HqRrJmTZI22TXQD/hef/gHRyscv00cnEK5uRaiQ5JXXIEQMxdRTmj5+fWzPhag xwsdlDfCy6SlE+x9yeo970ZkfQLp1W118ukE8+sQHVLeN+r9DqaHQ8y8jpBJhvED zwnDCD5yvLL2jGZTnHOR9r8i44COhkXoU2ce62RbW0k=; X-AuditID: c39127d2-253ff70000001c25-f5-5f6da157af91 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id DD.A5.07205.751AD6F5; Fri, 25 Sep 2020 09:50:47 +0200 (CEST) Received: from lws-riedmueller.phytec.de ([172.16.23.108]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2020092509504720-495333 ; Fri, 25 Sep 2020 09:50:47 +0200 From: Stefan Riedmueller To: Laurent Pinchart Cc: Mauro Carvalho Chehab , Sakari Ailus , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Christian Hemp , Stefan Riedmueller Subject: [PATCH 4/5] media: mt9p031: Make pixel clock polarity configurable by DT Date: Fri, 25 Sep 2020 09:50:28 +0200 Message-Id: <20200925075029.32181-4-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200925075029.32181-1-s.riedmueller@phytec.de> References: <20200925075029.32181-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 25.09.2020 09:50:47, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 25.09.2020 09:50:47 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrALMWRmVeSWpSXmKPExsWyRoCBSzd8YW68wf7pihadE5ewW1zeNYfN omfDVlaLZZv+MFl82vKNyYHVY3bHTFaPTas62TzmnQz0+LxJLoAlissmJTUnsyy1SN8ugStj zrldrAWtUhXL5ncyNTD2inUxcnJICJhI3G2ezQxiCwlsY5R48Fmgi5ELyL7GKHGqaTkLSIJN wEhiwbRGJhBbRMBConfRdEaQImaB54wSc7bvYgRJCAsESvw7vIwdxGYRUJW48esSG4jNK2Aj 8XXTbFaIbfISMy99B6vhFLCVOPr2PBPEZhuJFzv+MkLUC0qcnPmEBWSBhMAVRomZh3qZIZqF JE4vPgtmMwtoSyxb+Jp5AqPALCQ9s5CkFjAyrWIUys1Mzk4tyszWK8ioLElN1ktJ3cQIDNXD E9Uv7WDsm+NxiJGJg/EQowQHs5II7/ENOfFCvCmJlVWpRfnxRaU5qcWHGKU5WJTEeTfwloQJ CaQnlqRmp6YWpBbBZJk4OKUaGA9wTRR0PiC+yMNiyhQdkW2tbqt9mHdqN2xwkP8YvOFHScuk TGFePYXa+w3qimIM63hKynedm9p1eHfu5sbsqjVNHcum1a19n9YQsiyG+e2tL+cCbz/zniyo 36n099SaFeHmH28Iyx69vNBxwxVJrs6VaVPC2g0ObVfjeOP9ofaL6ZaOne/dapVYijMSDbWY i4oTAVrdt5xDAgAA Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Christian Hemp Evaluate the desired pixel clock polarity from the device tree. Signed-off-by: Christian Hemp Signed-off-by: Stefan Riedmueller --- drivers/media/i2c/Kconfig | 1 + drivers/media/i2c/mt9p031.c | 19 ++++++++++++++++++- include/media/i2c/mt9p031.h | 1 + 3 files changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index c7ba76fee599..7c026daeacf0 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -1103,6 +1103,7 @@ config VIDEO_MT9P031 select MEDIA_CONTROLLER select VIDEO_V4L2_SUBDEV_API select VIDEO_APTINA_PLL + select V4L2_FWNODE help This is a Video4Linux2 sensor driver for the Aptina (Micron) mt9p031 5 Mpixel camera. diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index f5d6a7890c47..8f8ee37a2dd2 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include "aptina-pll.h" @@ -399,6 +400,14 @@ static int __mt9p031_set_power(struct mt9p031 *mt9p031, bool on) return ret; } + /* Configure the pixel clock polarity */ + if (mt9p031->pdata && mt9p031->pdata->pixclk_pol) { + ret = mt9p031_write(client, MT9P031_PIXEL_CLOCK_CONTROL, + MT9P031_PIXEL_CLOCK_INVERT); + if (ret < 0) + return ret; + } + return v4l2_ctrl_handler_setup(&mt9p031->ctrls); } @@ -1062,7 +1071,8 @@ static const struct v4l2_subdev_internal_ops mt9p031_subdev_internal_ops = { static struct mt9p031_platform_data * mt9p031_get_pdata(struct i2c_client *client) { - struct mt9p031_platform_data *pdata; + struct mt9p031_platform_data *pdata = NULL; + struct v4l2_fwnode_endpoint endpoint; struct device_node *np; if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node) @@ -1072,6 +1082,10 @@ mt9p031_get_pdata(struct i2c_client *client) if (!np) return NULL; + endpoint.bus_type = V4L2_MBUS_UNKNOWN; + if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0) + goto done; + pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) goto done; @@ -1079,6 +1093,9 @@ mt9p031_get_pdata(struct i2c_client *client) of_property_read_u32(np, "input-clock-frequency", &pdata->ext_freq); of_property_read_u32(np, "pixel-clock-frequency", &pdata->target_freq); + pdata->pixclk_pol = !!(endpoint.bus.parallel.flags & + V4L2_MBUS_PCLK_SAMPLE_RISING); + done: of_node_put(np); return pdata; diff --git a/include/media/i2c/mt9p031.h b/include/media/i2c/mt9p031.h index 7c29c53aa988..f933cd0be8e5 100644 --- a/include/media/i2c/mt9p031.h +++ b/include/media/i2c/mt9p031.h @@ -10,6 +10,7 @@ struct v4l2_subdev; * @target_freq: Pixel clock frequency */ struct mt9p031_platform_data { + unsigned int pixclk_pol:1; int ext_freq; int target_freq; };