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Tue, 29 Jun 2021 08:21:42 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 01/13] dt-bindings: media: imx8q: add imx video codec bindings Date: Tue, 29 Jun 2021 16:21:02 +0800 Message-Id: <201c608e24da92498fde48708afa2dedde5c8f0b.1624954576.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: X-Originating-IP: [119.31.174.70] X-ClientProxiedBy: SG2PR06CA0160.apcprd06.prod.outlook.com (2603:1096:1:1e::14) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SG2PR06CA0160.apcprd06.prod.outlook.com (2603:1096:1:1e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.19 via Frontend Transport; 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Implement via mailbox on driver. + $ref: ../mailbox/fsl,mu.yaml# + + + "^vpu_core@[0-9a-f]+$": + description: + Each core correspond a decoder or encoder, need to configure them + separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC + has one decoder and one encoder. + type: object + + properties: + compatible: + oneOf: + - const: nxp,imx8q-vpu-decoder + - const: nxp,imx8q-vpu-encoder + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + mbox-names: + items: + - const: tx0 + - const: tx1 + - const: rx + + mboxes: + description: + List of phandle of 2 MU channels for tx, 1 MU channel for rx. + maxItems: 1 + + nxp,boot-region: + description: + Phandle to a node describing reserved memory used by firmware + loading. + $ref: /schemas/types.yaml#/definitions/phandle + + nxp,rpc-region: + description: + Phandle to a node describing reserved memory used by RPC shared + memory between firmware and driver. + $ref: /schemas/types.yaml#/definitions/phandle + + nxp,print-offset: + description: + The memory offset from RPC address, used by reserve firmware log. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - compatible + - reg + - power-domains + - mbox-names + - mboxes + - nxp,boot-region + - nxp,rpc-region + - nxp,print-offset + + additionalProperties: false + +required: + - compatible + - reg + - power-domains + - memory-region + +additionalProperties: true + +examples: + # Device node example for i.MX8QM platform: + - | + #include + + vpu: vpu@2c000000 { + compatible = "nxp,imx8qm-vpu"; + ranges = <0x2c000000 0x2c000000 0x2000000>; + reg = <0x2c000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&pd IMX_SC_R_VPU>; + memory-region = <&vpu_reserved>; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = <0 472 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = <0 473 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = <0 474 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + }; + + vpu_core0: vpu_core@2d080000 { + compatible = "nxp,imx8q-vpu-decoder"; + reg = <0x2d080000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0 + &mu_m0 0 1 + &mu_m0 1 0>; + nxp,boot-region = <&decoder_boot>; + nxp,rpc-region = <&decoder_rpc>; + nxp,print-offset = <0x180000>; + }; + + vpu_core1: vpu_core@2d090000 { + compatible = "nxp,imx8q-vpu-encoder"; + reg = <0x2d090000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0>; + nxp,boot-region = <&encoder1_boot>; + nxp,rpc-region = <&encoder1_rpc>; + nxp,print-offset = <0x80000>; + }; + + vpu_core2: vpu_core@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0 + &mu2_m0 0 1 + &mu2_m0 1 0>; + nxp,boot-region = <&encoder2_boot>; + nxp,rpc-region = <&encoder2_rpc>; + nxp,print-offset = <0x80000>; + }; + }; + +...