diff mbox series

[v3,01/13] dt-bindings: media: imx8q: add imx video codec bindings

Message ID 201c608e24da92498fde48708afa2dedde5c8f0b.1624954576.git.ming.qian@nxp.com
State New
Headers show
Series imx8q video decoder/encoder driver | expand

Commit Message

Ming Qian June 29, 2021, 8:21 a.m. UTC
Add devicetree binding documentation for IMX8Q Video Processing Unit IP

Signed-off-by: Ming Qian <ming.qian@nxp.com>
Signed-off-by: Shijie Qin <shijie.qin@nxp.com>
Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>
---
 .../bindings/media/nxp,imx8q-vpu.yaml         | 191 ++++++++++++++++++
 1 file changed, 191 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml

Comments

Rob Herring July 14, 2021, 9:04 p.m. UTC | #1
On Tue, Jun 29, 2021 at 04:21:02PM +0800, Ming Qian wrote:
> Add devicetree binding documentation for IMX8Q Video Processing Unit IP

> 

> Signed-off-by: Ming Qian <ming.qian@nxp.com>

> Signed-off-by: Shijie Qin <shijie.qin@nxp.com>

> Signed-off-by: Zhou Peng <eagle.zhou@nxp.com>

> ---

>  .../bindings/media/nxp,imx8q-vpu.yaml         | 191 ++++++++++++++++++

>  1 file changed, 191 insertions(+)

>  create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml

> 

> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml

> new file mode 100644

> index 000000000000..b9e38caf3d10

> --- /dev/null

> +++ b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml

> @@ -0,0 +1,191 @@

> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

> +

> +%YAML 1.2

> +---

> +$id: http://devicetree.org/schemas/media/nxp,imx8q-vpu.yaml#

> +$schema: http://devicetree.org/meta-schemas/core.yaml#

> +

> +title: NXP i.MX8Q video encode and decode accelerators

> +

> +maintainers:

> +  - Ming Qian <ming.qian@nxp.com>

> +  - Shijie Qin <shijie.qin@nxp.com>

> +

> +description: |-

> +  The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present

> +  on NXP i.MX8Q SoCs.

> +

> +properties:

> +  $nodename:

> +    pattern: "^vpu@[0-9a-f]+$"

> +

> +  compatible:

> +    oneOf:

> +      - const: nxp,imx8qm-vpu

> +      - const: nxp,imx8qxp-vpu

> +

> +  reg:

> +    maxItems: 1

> +

> +  power-domains:

> +    maxItems: 1

> +

> +  memory-region:

> +    description:

> +      Phandle to a node describing reserved memory used by VPU.

> +      (see bindings/reserved-memory/reserved-memory.txt)


How many?

> +

> +patternProperties:

> +  "^mailbox@[0-9a-f]+$":

> +    description:

> +      Each vpu encoder or decoder correspond a MU, which used for communication

> +      between driver and firmware. Implement via mailbox on driver.

> +    $ref: ../mailbox/fsl,mu.yaml#

> +

> +

> +  "^vpu_core@[0-9a-f]+$":

> +    description:

> +      Each core correspond a decoder or encoder, need to configure them

> +      separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC

> +      has one decoder and one encoder.

> +    type: object

> +

> +    properties:

> +      compatible:

> +        oneOf:

> +          - const: nxp,imx8q-vpu-decoder

> +          - const: nxp,imx8q-vpu-encoder

> +

> +      reg:

> +        maxItems: 1

> +

> +      power-domains:

> +        maxItems: 1

> +

> +      mbox-names:

> +        items:

> +          - const: tx0

> +          - const: tx1

> +          - const: rx

> +

> +      mboxes:

> +        description:

> +          List of phandle of 2 MU channels for tx, 1 MU channel for rx.

> +        maxItems: 1

> +

> +      nxp,boot-region:

> +        description:

> +          Phandle to a node describing reserved memory used by firmware

> +          loading.

> +        $ref: /schemas/types.yaml#/definitions/phandle


'memory-region' is what points to reserved regions. If you have more 
than one, then you need to define what each index is.

> +

> +      nxp,rpc-region:

> +        description:

> +          Phandle to a node describing reserved memory used by RPC shared

> +          memory between firmware and driver.

> +        $ref: /schemas/types.yaml#/definitions/phandle

> +

> +      nxp,print-offset:

> +        description:

> +          The memory offset from RPC address, used by reserve firmware log.

> +        $ref: /schemas/types.yaml#/definitions/uint32

> +

> +    required:

> +      - compatible

> +      - reg

> +      - power-domains

> +      - mbox-names

> +      - mboxes

> +      - nxp,boot-region

> +      - nxp,rpc-region

> +      - nxp,print-offset

> +

> +    additionalProperties: false

> +

> +required:

> +  - compatible

> +  - reg

> +  - power-domains

> +  - memory-region

> +

> +additionalProperties: true


Nope. 'true' is only acceptible for common bindings.

> +

> +examples:

> +  # Device node example for i.MX8QM platform:

> +  - |

> +    #include <dt-bindings/firmware/imx/rsrc.h>

> +

> +    vpu: vpu@2c000000 {

> +      compatible = "nxp,imx8qm-vpu";

> +      ranges = <0x2c000000 0x2c000000 0x2000000>;

> +      reg = <0x2c000000 0x1000000>;

> +      #address-cells = <1>;

> +      #size-cells = <1>;

> +      power-domains = <&pd IMX_SC_R_VPU>;

> +      memory-region = <&vpu_reserved>;

> +

> +      mu_m0: mailbox@2d000000 {

> +        compatible = "fsl,imx6sx-mu";

> +        reg = <0x2d000000 0x20000>;

> +        interrupts = <0 472 4>;

> +        #mbox-cells = <2>;

> +        power-domains = <&pd IMX_SC_R_VPU_MU_0>;

> +      };

> +

> +      mu1_m0: mailbox@2d020000 {

> +        compatible = "fsl,imx6sx-mu";

> +        reg = <0x2d020000 0x20000>;

> +        interrupts = <0 473 4>;

> +        #mbox-cells = <2>;

> +        power-domains = <&pd IMX_SC_R_VPU_MU_1>;

> +      };

> +

> +      mu2_m0: mailbox@2d040000 {

> +        compatible = "fsl,imx6sx-mu";

> +        reg = <0x2d040000 0x20000>;

> +        interrupts = <0 474 4>;

> +        #mbox-cells = <2>;

> +        power-domains = <&pd IMX_SC_R_VPU_MU_2>;

> +      };

> +

> +      vpu_core0: vpu_core@2d080000 {

> +        compatible = "nxp,imx8q-vpu-decoder";

> +        reg = <0x2d080000 0x10000>;

> +        power-domains = <&pd IMX_SC_R_VPU_DEC_0>;

> +        mbox-names = "tx0", "tx1", "rx";

> +        mboxes = <&mu_m0 0 0

> +                  &mu_m0 0 1

> +                  &mu_m0 1 0>;

> +        nxp,boot-region = <&decoder_boot>;

> +        nxp,rpc-region = <&decoder_rpc>;

> +        nxp,print-offset = <0x180000>;

> +      };

> +

> +      vpu_core1: vpu_core@2d090000 {

> +        compatible = "nxp,imx8q-vpu-encoder";

> +        reg = <0x2d090000 0x10000>;

> +        power-domains = <&pd IMX_SC_R_VPU_ENC_0>;

> +        mbox-names = "tx0", "tx1", "rx";

> +        mboxes = <&mu1_m0 0 0

> +                  &mu1_m0 0 1

> +                  &mu1_m0 1 0>;

> +        nxp,boot-region = <&encoder1_boot>;

> +        nxp,rpc-region = <&encoder1_rpc>;

> +        nxp,print-offset = <0x80000>;

> +      };

> +

> +      vpu_core2: vpu_core@2d0a0000 {

> +        reg = <0x2d0a0000 0x10000>;

> +        compatible = "nxp,imx8q-vpu-encoder";

> +        power-domains = <&pd IMX_SC_R_VPU_ENC_1>;

> +        mbox-names = "tx0", "tx1", "rx";

> +        mboxes = <&mu2_m0 0 0

> +                  &mu2_m0 0 1

> +                  &mu2_m0 1 0>;

> +        nxp,boot-region = <&encoder2_boot>;

> +        nxp,rpc-region = <&encoder2_rpc>;

> +        nxp,print-offset = <0x80000>;

> +      };

> +    };

> +

> +...

> -- 

> 2.31.1

> 

>
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
new file mode 100644
index 000000000000..b9e38caf3d10
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml
@@ -0,0 +1,191 @@ 
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/nxp,imx8q-vpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8Q video encode and decode accelerators
+
+maintainers:
+  - Ming Qian <ming.qian@nxp.com>
+  - Shijie Qin <shijie.qin@nxp.com>
+
+description: |-
+  The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present
+  on NXP i.MX8Q SoCs.
+
+properties:
+  $nodename:
+    pattern: "^vpu@[0-9a-f]+$"
+
+  compatible:
+    oneOf:
+      - const: nxp,imx8qm-vpu
+      - const: nxp,imx8qxp-vpu
+
+  reg:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+  memory-region:
+    description:
+      Phandle to a node describing reserved memory used by VPU.
+      (see bindings/reserved-memory/reserved-memory.txt)
+
+patternProperties:
+  "^mailbox@[0-9a-f]+$":
+    description:
+      Each vpu encoder or decoder correspond a MU, which used for communication
+      between driver and firmware. Implement via mailbox on driver.
+    $ref: ../mailbox/fsl,mu.yaml#
+
+
+  "^vpu_core@[0-9a-f]+$":
+    description:
+      Each core correspond a decoder or encoder, need to configure them
+      separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC
+      has one decoder and one encoder.
+    type: object
+
+    properties:
+      compatible:
+        oneOf:
+          - const: nxp,imx8q-vpu-decoder
+          - const: nxp,imx8q-vpu-encoder
+
+      reg:
+        maxItems: 1
+
+      power-domains:
+        maxItems: 1
+
+      mbox-names:
+        items:
+          - const: tx0
+          - const: tx1
+          - const: rx
+
+      mboxes:
+        description:
+          List of phandle of 2 MU channels for tx, 1 MU channel for rx.
+        maxItems: 1
+
+      nxp,boot-region:
+        description:
+          Phandle to a node describing reserved memory used by firmware
+          loading.
+        $ref: /schemas/types.yaml#/definitions/phandle
+
+      nxp,rpc-region:
+        description:
+          Phandle to a node describing reserved memory used by RPC shared
+          memory between firmware and driver.
+        $ref: /schemas/types.yaml#/definitions/phandle
+
+      nxp,print-offset:
+        description:
+          The memory offset from RPC address, used by reserve firmware log.
+        $ref: /schemas/types.yaml#/definitions/uint32
+
+    required:
+      - compatible
+      - reg
+      - power-domains
+      - mbox-names
+      - mboxes
+      - nxp,boot-region
+      - nxp,rpc-region
+      - nxp,print-offset
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - power-domains
+  - memory-region
+
+additionalProperties: true
+
+examples:
+  # Device node example for i.MX8QM platform:
+  - |
+    #include <dt-bindings/firmware/imx/rsrc.h>
+
+    vpu: vpu@2c000000 {
+      compatible = "nxp,imx8qm-vpu";
+      ranges = <0x2c000000 0x2c000000 0x2000000>;
+      reg = <0x2c000000 0x1000000>;
+      #address-cells = <1>;
+      #size-cells = <1>;
+      power-domains = <&pd IMX_SC_R_VPU>;
+      memory-region = <&vpu_reserved>;
+
+      mu_m0: mailbox@2d000000 {
+        compatible = "fsl,imx6sx-mu";
+        reg = <0x2d000000 0x20000>;
+        interrupts = <0 472 4>;
+        #mbox-cells = <2>;
+        power-domains = <&pd IMX_SC_R_VPU_MU_0>;
+      };
+
+      mu1_m0: mailbox@2d020000 {
+        compatible = "fsl,imx6sx-mu";
+        reg = <0x2d020000 0x20000>;
+        interrupts = <0 473 4>;
+        #mbox-cells = <2>;
+        power-domains = <&pd IMX_SC_R_VPU_MU_1>;
+      };
+
+      mu2_m0: mailbox@2d040000 {
+        compatible = "fsl,imx6sx-mu";
+        reg = <0x2d040000 0x20000>;
+        interrupts = <0 474 4>;
+        #mbox-cells = <2>;
+        power-domains = <&pd IMX_SC_R_VPU_MU_2>;
+      };
+
+      vpu_core0: vpu_core@2d080000 {
+        compatible = "nxp,imx8q-vpu-decoder";
+        reg = <0x2d080000 0x10000>;
+        power-domains = <&pd IMX_SC_R_VPU_DEC_0>;
+        mbox-names = "tx0", "tx1", "rx";
+        mboxes = <&mu_m0 0 0
+                  &mu_m0 0 1
+                  &mu_m0 1 0>;
+        nxp,boot-region = <&decoder_boot>;
+        nxp,rpc-region = <&decoder_rpc>;
+        nxp,print-offset = <0x180000>;
+      };
+
+      vpu_core1: vpu_core@2d090000 {
+        compatible = "nxp,imx8q-vpu-encoder";
+        reg = <0x2d090000 0x10000>;
+        power-domains = <&pd IMX_SC_R_VPU_ENC_0>;
+        mbox-names = "tx0", "tx1", "rx";
+        mboxes = <&mu1_m0 0 0
+                  &mu1_m0 0 1
+                  &mu1_m0 1 0>;
+        nxp,boot-region = <&encoder1_boot>;
+        nxp,rpc-region = <&encoder1_rpc>;
+        nxp,print-offset = <0x80000>;
+      };
+
+      vpu_core2: vpu_core@2d0a0000 {
+        reg = <0x2d0a0000 0x10000>;
+        compatible = "nxp,imx8q-vpu-encoder";
+        power-domains = <&pd IMX_SC_R_VPU_ENC_1>;
+        mbox-names = "tx0", "tx1", "rx";
+        mboxes = <&mu2_m0 0 0
+                  &mu2_m0 0 1
+                  &mu2_m0 1 0>;
+        nxp,boot-region = <&encoder2_boot>;
+        nxp,rpc-region = <&encoder2_rpc>;
+        nxp,print-offset = <0x80000>;
+      };
+    };
+
+...