From patchwork Thu Aug 6 19:01:34 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 256235 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 952B1C433E1 for ; Thu, 6 Aug 2020 19:02:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id CDAD3206C3 for ; Thu, 6 Aug 2020 19:02:13 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="octD1zCU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729601AbgHFTCH (ORCPT ); Thu, 6 Aug 2020 15:02:07 -0400 Received: from hqnvemgate24.nvidia.com ([216.228.121.143]:7224 "EHLO hqnvemgate24.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729339AbgHFTBs (ORCPT ); Thu, 6 Aug 2020 15:01:48 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate24.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 06 Aug 2020 12:00:06 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 06 Aug 2020 12:01:46 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 06 Aug 2020 12:01:46 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 6 Aug 2020 19:01:46 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Thu, 6 Aug 2020 19:01:45 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.172.190]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 06 Aug 2020 12:01:45 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , Subject: [PATCH v9 10/10] media: tegra-video: Compute settle times based on the clock rate Date: Thu, 6 Aug 2020 12:01:34 -0700 Message-ID: <1596740494-19306-11-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596740494-19306-1-git-send-email-skomatineni@nvidia.com> References: <1596740494-19306-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596740406; bh=R+T0KC4vw19h7jSpIlBRjG2YD+QkrkwInU94vYDC9nc=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=octD1zCUYMomt1dds3NFRXWr8Fky9BeAbeII0cDvoWBaFRjZypTBWtP9MPrlW+LA6 RIKeDlHxiW8QcKbKX8yliohMSbaw58XpASqEC74Z0E42c8HAwIRitdu3P9Lwxwq+yH NDzjDZjfjizYDthYdr8cj0PSiEzgiTlXYoCV2QEN95fo3OCj4rdkbqs8W0Q82T9E66 uHOC5yMTMpx7eRN6Wkq3KBGZUQE2mYUfAVIJBkLt7XN5mCRZcKobL9JVAmnpxb41oc EVsgsmaNgnVkVLJ8fO0/xq6NHifuLUR62ZJmiGk99TLSMbu+1RP195oJTAqePgQyW/ TEpC9N4hTzbmA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Settle time determines the number of cil clock cyles to wait after LP00 when moving from LP to HS. This patch computes T-CLK-SETTLE and T-HS-SETTLE times based on cil clock rate and pixel rate from the sensor and programs them during streaming. T-CLK-SETTLE time is the interval during which receiver will ignore any HS transitions on clock lane starting from the beginning of T-CLK-PREPARE. T-HS-SETTLE time is the interval during which recevier will ignore any HS transitions on data lane starting from the beginning of T-HS-PREPARE. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/TODO | 1 - drivers/staging/media/tegra-video/csi.c | 55 ++++++++++++++++++++++++++++ drivers/staging/media/tegra-video/csi.h | 5 +++ drivers/staging/media/tegra-video/tegra210.c | 17 ++++++++- 4 files changed, 75 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/tegra-video/TODO b/drivers/staging/media/tegra-video/TODO index 98d3c7d..c821081 100644 --- a/drivers/staging/media/tegra-video/TODO +++ b/drivers/staging/media/tegra-video/TODO @@ -1,5 +1,4 @@ TODO list -* Add MIPI clock Settle time computation based on the data rate. * Add support for Ganged mode. * Add RAW10 packed video format support to Tegra210 video formats. * Add support for suspend and resume. diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/media/tegra-video/csi.c index 7e154f9..a19c85c 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -19,6 +19,8 @@ #include "csi.h" #include "video.h" +#define MHZ 1000000 + static inline struct tegra_csi * host1x_client_to_csi(struct host1x_client *client) { @@ -235,6 +237,59 @@ static int tegra_csi_g_frame_interval(struct v4l2_subdev *subdev, return 0; } +static unsigned int csi_get_pixel_rate(struct tegra_csi_channel *csi_chan) +{ + struct tegra_vi_channel *chan; + struct v4l2_subdev *src_subdev; + struct v4l2_ctrl *ctrl; + + chan = v4l2_get_subdev_hostdata(&csi_chan->subdev); + src_subdev = tegra_channel_get_remote_source_subdev(chan); + ctrl = v4l2_ctrl_find(src_subdev->ctrl_handler, V4L2_CID_PIXEL_RATE); + if (ctrl) + return v4l2_ctrl_g_ctrl_int64(ctrl); + + return 0; +} + +void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, + u8 *clk_settle_time, + u8 *ths_settle_time) +{ + struct tegra_csi *csi = csi_chan->csi; + unsigned int cil_clk_mhz; + unsigned int pix_clk_mhz; + int clk_idx = (csi_chan->csi_port_num >> 1) + 1; + + cil_clk_mhz = clk_get_rate(csi->clks[clk_idx].clk) / MHZ; + pix_clk_mhz = csi_get_pixel_rate(csi_chan) / MHZ; + + /* + * CLK Settle time is the interval during which HS receiver should + * ignore any clock lane HS transitions, starting from the beginning + * of T-CLK-PREPARE. + * Per DPHY specification, T-CLK-SETTLE should be between 95ns ~ 300ns + * + * 95ns < (clk-settle-programmed + 7) * lp clk period < 300ns + * midpoint = 197.5 ns + */ + *clk_settle_time = ((95 + 300) * cil_clk_mhz - 14000) / 2000; + + /* + * THS Settle time is the interval during which HS receiver should + * ignore any data lane HS transitions, starting from the beginning + * of THS-PREPARE. + * + * Per DPHY specification, T-HS-SETTLE should be between 85ns + 6UI + * and 145ns+10UI. + * 85ns + 6UI < (Ths-settle-prog + 5) * lp_clk_period < 145ns + 10UI + * midpoint = 115ns + 8UI + */ + if (pix_clk_mhz) + *ths_settle_time = (115 * cil_clk_mhz + 8000 * cil_clk_mhz + / (2 * pix_clk_mhz) - 5000) / 1000; +} + static int tegra_csi_enable_stream(struct v4l2_subdev *subdev) { struct tegra_vi_channel *chan = v4l2_get_subdev_hostdata(subdev); diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/media/tegra-video/csi.h index 0d50fc3..c65ff73 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -51,6 +51,7 @@ struct tegra_csi; * @h_blank: horizontal blanking for TPG active format * @v_blank: vertical blanking for TPG active format * @mipi: mipi device for corresponding csi channel pads + * @pixel_rate: active pixel rate from the sensor on this channel */ struct tegra_csi_channel { struct list_head list; @@ -67,6 +68,7 @@ struct tegra_csi_channel { unsigned int h_blank; unsigned int v_blank; struct tegra_mipi_device *mipi; + unsigned int pixel_rate; }; /** @@ -147,4 +149,7 @@ extern const struct tegra_csi_soc tegra210_csi_soc; #endif void tegra_csi_error_recover(struct v4l2_subdev *subdev); +void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, + u8 *clk_settle_time, + u8 *ths_settle_time); #endif diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging/media/tegra-video/tegra210.c index 253bf33..ac066c0 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -7,6 +7,7 @@ * This source file contains Tegra210 supported video formats, * VI and CSI SoC specific data, operations and registers accessors. */ +#include #include #include #include @@ -98,6 +99,8 @@ #define BRICK_CLOCK_B_4X (0x2 << 16) #define TEGRA_CSI_CIL_PAD_CONFIG1 0x004 #define TEGRA_CSI_CIL_PHY_CONTROL 0x008 +#define CLK_SETTLE_MASK GENMASK(13, 8) +#define THS_SETTLE_MASK GENMASK(5, 0) #define TEGRA_CSI_CIL_INTERRUPT_MASK 0x00c #define TEGRA_CSI_CIL_STATUS 0x010 #define TEGRA_CSI_CILX_STATUS 0x014 @@ -770,8 +773,14 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) { struct tegra_csi *csi = csi_chan->csi; unsigned int portno = csi_chan->csi_port_num; + u8 clk_settle_time = 0; + u8 ths_settle_time = 10; u32 val; + if (!csi_chan->pg_mode) + tegra_csi_calc_settle_time(csi_chan, &clk_settle_time, + &ths_settle_time); + csi_write(csi, portno, TEGRA_CSI_CLKEN_OVERRIDE, 0); /* clean up status */ @@ -782,7 +791,9 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) /* CIL PHY registers setup */ cil_write(csi, portno, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0); - cil_write(csi, portno, TEGRA_CSI_CIL_PHY_CONTROL, 0xa); + cil_write(csi, portno, TEGRA_CSI_CIL_PHY_CONTROL, + FIELD_PREP(CLK_SETTLE_MASK, clk_settle_time) | + FIELD_PREP(THS_SETTLE_MASK, ths_settle_time)); /* * The CSI unit provides for connection of up to six cameras in @@ -801,7 +812,9 @@ static int tegra210_csi_start_streaming(struct tegra_csi_channel *csi_chan) BRICK_CLOCK_A_4X); cil_write(csi, portno + 1, TEGRA_CSI_CIL_PAD_CONFIG0, 0x0); cil_write(csi, portno + 1, TEGRA_CSI_CIL_INTERRUPT_MASK, 0x0); - cil_write(csi, portno + 1, TEGRA_CSI_CIL_PHY_CONTROL, 0xa); + cil_write(csi, portno + 1, TEGRA_CSI_CIL_PHY_CONTROL, + FIELD_PREP(CLK_SETTLE_MASK, clk_settle_time) | + FIELD_PREP(THS_SETTLE_MASK, ths_settle_time)); csi_write(csi, portno, TEGRA_CSI_PHY_CIL_COMMAND, CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_ENABLE); } else {