From patchwork Sun Mar 15 01:45:59 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 210620 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3006C5ACC1 for ; Sun, 15 Mar 2020 01:46:55 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B9C1A2076D for ; Sun, 15 Mar 2020 01:46:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="kLFzp45z" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727229AbgCOBqG (ORCPT ); Sat, 14 Mar 2020 21:46:06 -0400 Received: from hqnvemgate25.nvidia.com ([216.228.121.64]:4222 "EHLO hqnvemgate25.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726988AbgCOBqF (ORCPT ); Sat, 14 Mar 2020 21:46:05 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate25.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sat, 14 Mar 2020 18:45:18 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sat, 14 Mar 2020 18:46:05 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sat, 14 Mar 2020 18:46:05 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Sun, 15 Mar 2020 01:46:04 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Sun, 15 Mar 2020 01:46:04 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.175.141]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sat, 14 Mar 2020 18:46:04 -0700 From: Sowjanya Komatineni To: , , , , , , CC: , , , , Subject: [RFC PATCH v4 1/8] arm64: tegra: Fix sor powergate clocks and reset Date: Sat, 14 Mar 2020 18:45:59 -0700 Message-ID: <1584236766-24819-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1584236766-24819-1-git-send-email-skomatineni@nvidia.com> References: <1584236766-24819-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1584236718; bh=PTc2SyRS9NP+68XdMh+c6cj6nLmKTNHZwxALx6dnzdM=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=kLFzp45zhZwEq1wWj+FOe8Bu5pDofUz0uTd3bOzNMvK+xHa2Iuho9C77N5S7JDKw9 ZFjLIYP+guGkOym4oRFnaORuALZEKA6ql6sOE6Mk+hWgRRFzOE7O9DhrwQ7tO2Dsho /yUvLRfJpHXQhrMMwzUKJium93zysGfrrANEsAde1W4IotBu+/AFWmDyMSROiq0rHZ ktUSDjfwWbBscCCWdZBfASviLV/XnIvZSG4ZRqpdPsAtgMnD3+7NyprsFSWLSqBjBe Fd2ZyeZKU1lW0k5SjqWMhR6zHY2IGPbaaqUXNW7I7i/z6zInuiQf4B6idj0fiJ+LEm ixzdclHdf52lQ== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Tegra210 device tree lists csi clock and reset under SOR powergate node. But Tegra210 has csicil in SOR partition and csi in VENC partition. So, this patch includes fix for sor powergate node. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index 64c46ce..d0eff92 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -796,7 +796,9 @@ pd_sor: sor { clocks = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, + <&tegra_car TEGRA210_CLK_CILAB>, + <&tegra_car TEGRA210_CLK_CILCD>, + <&tegra_car TEGRA210_CLK_CILE>, <&tegra_car TEGRA210_CLK_DSIA>, <&tegra_car TEGRA210_CLK_DSIB>, <&tegra_car TEGRA210_CLK_DPAUX>, @@ -804,7 +806,6 @@ <&tegra_car TEGRA210_CLK_MIPI_CAL>; resets = <&tegra_car TEGRA210_CLK_SOR0>, <&tegra_car TEGRA210_CLK_SOR1>, - <&tegra_car TEGRA210_CLK_CSI>, <&tegra_car TEGRA210_CLK_DSIA>, <&tegra_car TEGRA210_CLK_DSIB>, <&tegra_car TEGRA210_CLK_DPAUX>,