| Message ID | 20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org |
|---|---|
| Headers | show |
| Series | Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon | expand |
Hi Bryan. On 1/2/25 18:32, Bryan O'Donoghue wrote: > Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration > of previous CAMCC blocks with the exception of having two required > power-domains not just one. > > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index c18b99765c25c901b3d0a3fbaddc320c0a8c1716..5c7b0c048d41a4ba3d74bbf77216ad09b652ed30 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -5,6 +5,7 @@ > > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> > +#include <dt-bindings/clock/qcom,x1e80100-camcc.h> > #include <dt-bindings/clock/qcom,x1e80100-dispcc.h> > #include <dt-bindings/clock/qcom,x1e80100-gcc.h> > #include <dt-bindings/clock/qcom,x1e80100-gpucc.h> > @@ -4647,6 +4648,21 @@ usb_1_ss1_dwc3_ss: endpoint { > }; > }; > > + camcc: clock-controller@ade0000 { > + compatible = "qcom,x1e80100-camcc"; > + reg = <0 0x0ade0000 0 0x20000>; > + clocks = <&gcc GCC_CAMERA_AHB_CLK>, > + <&bi_tcxo_div2>, > + <&bi_tcxo_ao_div2>, > + <&sleep_clk>; > + power-domains = <&rpmhpd RPMHPD_MXC>, > + <&rpmhpd RPMHPD_MMCX>; > + required-opps = <&rpmhpd_opp_low_svs>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > mdss: display-subsystem@ae00000 { > compatible = "qcom,x1e80100-mdss"; > reg = <0 0x0ae00000 0 0x1000>; > Looks good, thank you. Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> -- Best wishes, Vladimir
On 1/2/25 18:32, Bryan O'Donoghue wrote: > Add dtsi to describe the xe180100 CAMSS block > > 4 x CSIPHY > 2 x CSID > 2 x CSID Lite > 2 x IFE > 2 x IFE Lite > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 185 +++++++++++++++++++++++++++++++++ > 1 file changed, 185 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 97ebf5596dfc3caa920ef85722ca8afd49cd3c24..0b5b48d2c59e0b18816ea131e0f687b8bf84e1da 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -4726,6 +4726,191 @@ cci1_i2c1: i2c-bus@1 { > }; > }; > > + camss: isp@acb6000 { > + compatible = "qcom,x1e80100-camss"; > + > + reg = <0 0x0acb6000 0 0x1000>, > + <0 0x0acb7000 0 0x2000>, > + <0 0x0acb9000 0 0x2000>, > + <0 0x0acbb000 0 0x2000>, > + <0 0x0acc6000 0 0x1000>, > + <0 0x0acca000 0 0x1000>, > + <0 0x0ace4000 0 0x2000>, > + <0 0x0ace6000 0 0x2000>, > + <0 0x0ace8000 0 0x2000>, > + <0 0x0acec000 0 0x2000>, > + <0 0x0acf6000 0 0x1000>, > + <0 0x0acf7000 0 0x1000>, > + <0 0x0acf8000 0 0x1000>, > + <0 0x0acc7000 0 0x2000>, > + <0 0x0accb000 0 0x2000>, > + <0 0x0ac62000 0 0x4000>, > + <0 0x0ac71000 0 0x4000>; > + reg-names = "csid_wrapper", > + "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy4", > + "csitpg0", > + "csitpg1", > + "csitpg2", > + "vfe_lite0", > + "vfe_lite1", > + "vfe0", > + "vfe1"; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>, > + <&camcc CAM_CC_CORE_AHB_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, > + <&camcc CAM_CC_CPAS_IFE_0_CLK>, > + <&camcc CAM_CC_CPAS_IFE_1_CLK>, > + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, > + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, > + <&camcc CAM_CC_CSID_CLK>, > + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, > + <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY1_CLK>, > + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY2_CLK>, > + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, > + <&camcc CAM_CC_CSIPHY4_CLK>, > + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&gcc GCC_CAMERA_SF_AXI_CLK>, > + <&camcc CAM_CC_IFE_0_CLK>, > + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_1_CLK>, > + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CLK>, > + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, > + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, > + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; > + clock-names = "camnoc_rt_axi", > + "camnoc_nrt_axi", > + "core_ahb", > + "cpas_ahb", > + "cpas_fast_ahb", > + "cpas_vfe0", > + "cpas_vfe1", > + "cpas_vfe_lite", > + "cphy_rx_clk_src", > + "csid", > + "csid_csiphy_rx", > + "csiphy0", > + "csiphy0_timer", > + "csiphy1", > + "csiphy1_timer", > + "csiphy2", > + "csiphy2_timer", > + "csiphy4", > + "csiphy4_timer", > + "gcc_axi_hf", > + "gcc_axi_sf", > + "vfe0", > + "vfe0_fast_ahb", > + "vfe1", > + "vfe1_fast_ahb", > + "vfe_lite", > + "vfe_lite_ahb", > + "vfe_lite_cphy_rx", > + "vfe_lite_csid"; > + > + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy4", > + "vfe0", > + "vfe1", > + "vfe_lite0", > + "vfe_lite1"; > + > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, > + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "cam_ahb", > + "cam_hf_mnoc", > + "cam_sf_mnoc", > + "cam_sf_icp_mnoc"; > + > + iommus = <&apps_smmu 0x800 0x60>, > + <&apps_smmu 0x860 0x60>, > + <&apps_smmu 0x1800 0x60>, > + <&apps_smmu 0x1860 0x60>, > + <&apps_smmu 0x18e0 0x00>, > + <&apps_smmu 0x1900 0x00>, > + <&apps_smmu 0x1980 0x20>, > + <&apps_smmu 0x19a0 0x20>; > + > + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, > + <&camcc CAM_CC_IFE_1_GDSC>, > + <&camcc CAM_CC_TITAN_TOP_GDSC>; > + power-domain-names = "ife0", > + "ife1", > + "top"; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + port@1 { > + reg = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + port@2 { > + reg = <2>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + port@3 { > + reg = <3>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + }; > + > camcc: clock-controller@ade0000 { > compatible = "qcom,x1e80100-camcc"; > reg = <0 0x0ade0000 0 0x20000>; > Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> -- Best wishes, Vladimir
On 2.01.2025 5:32 PM, Bryan O'Donoghue wrote: > Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration > of previous CAMCC blocks with the exception of having two required > power-domains not just one. > > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Konrad
Hi Bryan, On Thu, Jan 02, 2025 at 04:32:06PM +0000, Bryan O'Donoghue wrote: > Add the x1e80100 CCI device string compatible. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> this patch 1/6 has already been merged in i2c/i2c-host. You should not send it anymore. The rest of the patches are handled elsewere. Thanks, Andi
v3: - Fixes ordering of headers in dtsi - Vlad - Changes camcc to always on - Vlad - Applies RB as indicated - Krzysztof, Konrad - Link to v2: https://lore.kernel.org/r/20241227-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v2-0-06fdd5a7d5bb@linaro.org v2: I've gone through each comment and implemented each suggestion since IMO they were all good/correct comments. Detail: - Moves x1e80100 camcc to its own yaml - Krzysztof - csid_wrapper comes first because it is the most relevant register set - configuring all CSID blocks subordinate to it - bod, Krzysztof - Fixes missing commit log - Krz - Updates to latest format established @ sc7280 - bod - Includes CSID lite which I forgot to add @ v1 - Konrad, bod - Replaces static ICC parameters with defines - Konrad - Drops newlines between x and x-name - Konrad - Drops redundant iommu extents - Konrad - Leaves CAMERA_AHB_CLK as-is - Kronrad, Dmitry Link: https://lore.kernel.org/r/3f1a960f-062e-4c29-ae7d-126192f35a8b@oss.qualcomm.com - Interrupt EDGE_RISING - Vladimir - Implements suggested regulator names pending refactor to PHY API - Vladimir - Drop slow_ahb_src clock - Vladimir Link to v1: https://lore.kernel.org/r/20241119-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v1-0-54075d75f654@linaro.org Working tree: https://git.codelinaro.org/bryan.odonoghue/kernel/-/tree/arm-laptop/wip/x1e80100-6.13-rc3 v1: This series adds dt-bindings and dtsi for CAMSS on x1e80100. The primary difference between x1e80100 and other platforms is a new VFE and CSID pair at version 680. Some minor driver churn will be required to support outside of the new VFE and CSID blocks but nothing too major. The CAMCC in this silicon requires two, not one power-domain requiring either this fix I've proposed here or something similar: https://lore.kernel.org/linux-arm-msm/bad60452-41b3-42fb-acba-5b7226226d2d@linaro.org/T/#t That doesn't gate adoption of the binding description though. A working tree in progress can be found here: https://git.codelinaro.org/bryan.odonoghue/kernel/-/tree/x1e80100-6.12-rc7+camss?ref_type=heads Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> --- Bryan O'Donoghue (6): dt-bindings: i2c: qcom-cci: Document x1e80100 compatible dt-bindings: clock: move qcom,x1e80100-camcc to its own file dt-bindings: media: Add qcom,x1e80100-camss arm64: dts: qcom: x1e80100: Add CAMCC block definition arm64: dts: qcom: x1e80100: Add CCI definitions arm64: dts: qcom: x1e80100: Add CAMSS block definition .../bindings/clock/qcom,sm8450-camcc.yaml | 2 - .../bindings/clock/qcom,x1e80100-camcc.yaml | 74 +++++ .../devicetree/bindings/i2c/qcom,i2c-cci.yaml | 2 + .../bindings/media/qcom,x1e80100-camss.yaml | 367 +++++++++++++++++++++ arch/arm64/boot/dts/qcom/x1e80100.dtsi | 351 ++++++++++++++++++++ 5 files changed, 794 insertions(+), 2 deletions(-) --- base-commit: e25c8d66f6786300b680866c0e0139981273feba change-id: 20241119-b4-linux-next-24-11-18-dtsi-x1e80100-camss-82a63736d072 Best regards,