| Message ID | 20241204100003.300123-1-quic_vikramsa@quicinc.com |
|---|---|
| Headers | show |
| Series | media: qcom: camss: Add sc7280 support | expand |
On Wed, Dec 04, 2024 at 03:29:59PM +0530, Vikram Sharma wrote: > Add bindings for qcom,sc7280-camss to support the camera subsystem > on the SC7280 platform. > > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > --- > .../bindings/media/qcom,sc7280-camss.yaml | 418 ++++++++++++++++++ > 1 file changed, 418 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml > ... > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,camcc-sc7280.h> > + #include <dt-bindings/clock/qcom,gcc-sc7280.h> > + #include <dt-bindings/interconnect/qcom,sc7280.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + camss@acb3000 { If there is going to be resend, then node name: isp Node names should be generic. See also an explanation and list of examples (not exhaustive) in DT specification: https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Best regards, Krzysztof
On 04/12/2024 09:59, Vikram Sharma wrote: > Add bindings for qcom,sc7280-camss to support the camera subsystem > on the SC7280 platform. > > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
On 05/12/2024 10:59, Vikram Sharma wrote: > Hi Krzysztof, > > Thanks for your "Reviewed-by" > > + camss@acb3000 { > > If there is going to be resend, then node name: isp > > Sure, we will change node-name from camss to isp or camera (As its a > part of generic names recommendation as per the shared link.) > If there is a resend. or we will address this as a followup. > > So > > - camss@acb3000 { > + camera@acb3000 { > > Best Regards, > Vikram Please no top-posting. https://subspace.kernel.org/etiquette.html Shouldn't that be isp@0xaddress ? If you are making this change, please remember to do it in both the example and the dts. --- bod
On 12/5/2024 5:26 PM, Bryan O'Donoghue wrote: > On 05/12/2024 10:59, Vikram Sharma wrote: >> Hi Krzysztof, >> >> Thanks for your "Reviewed-by" >> >> + camss@acb3000 { >> >> If there is going to be resend, then node name: isp >> >> Sure, we will change node-name from camss to isp or camera (As its a >> part of generic names recommendation as per the shared link.) >> If there is a resend. or we will address this as a followup. >> >> So >> >> - camss@acb3000 { >> + camera@acb3000 { >> >> Best Regards, >> Vikram > > Please no top-posting. > https://subspace.kernel.org/etiquette.html > > Shouldn't that be isp@0xaddress ? ACK. - camss@acb3000 { + isp@acb3000 { In both YAML and DTS. If we post V8. > > If you are making this change, please remember to do it in both the > example and the dts. Understood. Will avoid this. > > --- > bod Best Regards, Vikram
On 4.12.2024 11:00 AM, Vikram Sharma wrote: > The Vision Mezzanine for the RB3 ships with an imx577 camera sensor. > Enable the IMX577 on the vision mezzanine. > > An example media-ctl pipeline for the imx577 is: > > media-ctl --reset > media-ctl -v -V '"imx577 '19-001a'":0[fmt:SRGGB10/4056x3040 field:none]' > media-ctl -V '"msm_csiphy3":0[fmt:SRGGB10/4056x3040]' > media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' > media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' > media-ctl -l '"msm_csiphy3":1->"msm_csid0":0[1]' > media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' > > yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0 > > Signed-off-by: Hariram Purushothaman <quic_hariramp@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > --- [...] > +&camcc { > + status = "okay"; > +}; It's already enabled > + > +&camss { > + vdda-phy-supply = <&vreg_l10c_0p88>; > + vdda-pll-supply = <&vreg_l6b_1p2>; > + status = "okay"; A newline before status is expected > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* The port index denotes CSIPHY id i.e. csiphy3 */ > + port@3 { > + reg = <3>; > + csiphy3_ep: endpoint { Also between last property and subnode [...] > + > +&tlmm { > + cam2_default: cam2-default-state { > + rst-pins { > + pins = "gpio78"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + mclk-pins { > + pins = "gpio67"; > + function = "cam_mclk"; > + drive-strength = <2>; > + bias-disable; > + }; Please sort these by gpio idx Konrad
On Wed Dec 4, 2024 at 11:00 AM CET, Vikram Sharma wrote: > From: Suresh Vankadara <quic_svankada@quicinc.com> > > Add support for the camss driver on the sc7280 soc. > > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Hi Vikram, This is working on QCM6490 Fairphone 5 smartphone with WIP drivers for IMX858 and S5KJN1, thanks! Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 Regards Luca > --- > .../qcom/camss/camss-csiphy-3ph-1-0.c | 5 + > .../media/platform/qcom/camss/camss-csiphy.c | 5 + > .../media/platform/qcom/camss/camss-csiphy.h | 1 + > drivers/media/platform/qcom/camss/camss-vfe.c | 2 + > drivers/media/platform/qcom/camss/camss.c | 319 ++++++++++++++++++ > drivers/media/platform/qcom/camss/camss.h | 1 + > 6 files changed, 333 insertions(+) > > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > index 7d2490c9de01..f341f7b7fd8a 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > @@ -505,6 +505,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, > u32 val; > > switch (csiphy->camss->res->version) { > + case CAMSS_7280: > + r = &lane_regs_sm8250[0][0]; > + array_size = ARRAY_SIZE(lane_regs_sm8250[0]); > + break; > case CAMSS_8250: > r = &lane_regs_sm8250[0][0]; > array_size = ARRAY_SIZE(lane_regs_sm8250[0]); > @@ -557,6 +561,7 @@ static bool csiphy_is_gen2(u32 version) > bool ret = false; > > switch (version) { > + case CAMSS_7280: > case CAMSS_8250: > case CAMSS_8280XP: > case CAMSS_845: > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c > index 5af2b382a843..3791c2d8a6cf 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c > @@ -103,6 +103,11 @@ const struct csiphy_formats csiphy_formats_8x96 = { > .formats = formats_8x96 > }; > > +const struct csiphy_formats csiphy_formats_sc7280 = { > + .nformats = ARRAY_SIZE(formats_sdm845), > + .formats = formats_sdm845 > +}; > + > const struct csiphy_formats csiphy_formats_sdm845 = { > .nformats = ARRAY_SIZE(formats_sdm845), > .formats = formats_sdm845 > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h > index eebc1ff1cfab..b6209bddfb61 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy.h > +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h > @@ -111,6 +111,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy); > > extern const struct csiphy_formats csiphy_formats_8x16; > extern const struct csiphy_formats csiphy_formats_8x96; > +extern const struct csiphy_formats csiphy_formats_sc7280; > extern const struct csiphy_formats csiphy_formats_sdm845; > > extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0; > diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c > index fb3234c65403..95f6a1ac7eaf 100644 > --- a/drivers/media/platform/qcom/camss/camss-vfe.c > +++ b/drivers/media/platform/qcom/camss/camss-vfe.c > @@ -335,6 +335,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, > } > break; > case CAMSS_660: > + case CAMSS_7280: > case CAMSS_8x96: > case CAMSS_8250: > case CAMSS_8280XP: > @@ -1693,6 +1694,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) > int ret = 8; > > switch (vfe->camss->res->version) { > + case CAMSS_7280: > case CAMSS_8250: > case CAMSS_8280XP: > case CAMSS_845: > diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c > index f5704c23766a..4fa16ff6e614 100644 > --- a/drivers/media/platform/qcom/camss/camss.c > +++ b/drivers/media/platform/qcom/camss/camss.c > @@ -1266,6 +1266,310 @@ static const struct resources_icc icc_res_sm8250[] = { > }, > }; > > +static const struct camss_subdev_resources csiphy_res_7280[] = { > + /* CSIPHY0 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csiphy0", "csiphy0_timer" }, > + .clock_rate = { { 300000000, 400000000 }, > + { 300000000 } }, > + .reg = { "csiphy0" }, > + .interrupt = { "csiphy0" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY1 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csiphy1", "csiphy1_timer" }, > + .clock_rate = { { 300000000, 400000000 }, > + { 300000000 } }, > + .reg = { "csiphy1" }, > + .interrupt = { "csiphy1" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY2 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csiphy2", "csiphy2_timer" }, > + .clock_rate = { { 300000000, 400000000 }, > + { 300000000 } }, > + .reg = { "csiphy2" }, > + .interrupt = { "csiphy2" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY3 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csiphy3", "csiphy3_timer" }, > + .clock_rate = { { 300000000, 400000000 }, > + { 300000000 } }, > + .reg = { "csiphy3" }, > + .interrupt = { "csiphy3" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY4 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csiphy4", "csiphy4_timer" }, > + .clock_rate = { { 300000000, 400000000 }, > + { 300000000 } }, > + .reg = { "csiphy4" }, > + .interrupt = { "csiphy4" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > +}; > + > +static const struct camss_subdev_resources csid_res_7280[] = { > + /* CSID0 */ > + { > + .regulators = {}, > + > + .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0" }, > + .clock_rate = { { 300000000, 400000000 }, > + { 0 }, > + { 380000000, 510000000, 637000000, 760000000 } > + }, > + > + .reg = { "csid0" }, > + .interrupt = { "csid0" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID1 */ > + { > + .regulators = {}, > + > + .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1" }, > + .clock_rate = { { 300000000, 400000000 }, > + { 0 }, > + { 380000000, 510000000, 637000000, 760000000 } > + }, > + > + .reg = { "csid1" }, > + .interrupt = { "csid1" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID2 */ > + { > + .regulators = {}, > + > + .clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2" }, > + .clock_rate = { { 300000000, 400000000 }, > + { 0 }, > + { 380000000, 510000000, 637000000, 760000000 } > + }, > + > + .reg = { "csid2" }, > + .interrupt = { "csid2" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID3 */ > + { > + .regulators = {}, > + > + .clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" }, > + .clock_rate = { { 300000000, 400000000 }, > + { 0 }, > + { 320000000, 400000000, 480000000, 600000000 } > + }, > + > + .reg = { "csid_lite0" }, > + .interrupt = { "csid_lite0" }, > + .csid = { > + .is_lite = true, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID4 */ > + { > + .regulators = {}, > + > + .clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" }, > + .clock_rate = { { 300000000, 400000000 }, > + { 0 }, > + { 320000000, 400000000, 480000000, 600000000 } > + }, > + > + .reg = { "csid_lite1" }, > + .interrupt = { "csid_lite1" }, > + .csid = { > + .is_lite = true, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > +}; > + > +static const struct camss_subdev_resources vfe_res_7280[] = { > + /* VFE0 */ > + { > + .regulators = {}, > + > + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe0", > + "vfe0_axi", "gcc_cam_hf_axi" }, > + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, > + { 80000000 }, > + { 0 }, > + { 380000000, 510000000, 637000000, 760000000 }, > + { 0 }, > + { 0 } }, > + > + .reg = { "vfe0" }, > + .interrupt = { "vfe0" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .has_pd = true, > + .pd_name = "ife0", > + .hw_ops = &vfe_ops_170, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE1 */ > + { > + .regulators = {}, > + > + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe1", > + "vfe1_axi", "gcc_cam_hf_axi" }, > + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, > + { 80000000 }, > + { 0 }, > + { 380000000, 510000000, 637000000, 760000000 }, > + { 0 }, > + { 0 } }, > + > + .reg = { "vfe1" }, > + .interrupt = { "vfe1" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .has_pd = true, > + .pd_name = "ife1", > + .hw_ops = &vfe_ops_170, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE2 */ > + { > + .regulators = {}, > + > + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe2", > + "vfe2_axi", "gcc_cam_hf_axi" }, > + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, > + { 80000000 }, > + { 0 }, > + { 380000000, 510000000, 637000000, 760000000 }, > + { 0 }, > + { 0 } }, > + > + .reg = { "vfe2" }, > + .interrupt = { "vfe2" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .hw_ops = &vfe_ops_170, > + .has_pd = true, > + .pd_name = "ife2", > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE3 (lite) */ > + { > + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", > + "vfe_lite0", "gcc_cam_hf_axi" }, > + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, > + { 80000000 }, > + { 0 }, > + { 320000000, 400000000, 480000000, 600000000 }, > + { 0 } }, > + > + .regulators = {}, > + .reg = { "vfe_lite0" }, > + .interrupt = { "vfe_lite0" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_170, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE4 (lite) */ > + { > + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", > + "vfe_lite1", "gcc_cam_hf_axi" }, > + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, > + { 80000000 }, > + { 0 }, > + { 320000000, 400000000, 480000000, 600000000 }, > + { 0 } }, > + > + .regulators = {}, > + .reg = { "vfe_lite1" }, > + .interrupt = { "vfe_lite1" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_170, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > +}; > + > +static const struct resources_icc icc_res_sc7280[] = { > + { > + .name = "ahb", > + .icc_bw_tbl.avg = 38400, > + .icc_bw_tbl.peak = 76800, > + }, > + { > + .name = "hf_0", > + .icc_bw_tbl.avg = 2097152, > + .icc_bw_tbl.peak = 2097152, > + }, > +}; > + > static const struct camss_subdev_resources csiphy_res_sc8280xp[] = { > /* CSIPHY0 */ > { > @@ -2622,10 +2926,25 @@ static const struct camss_resources sc8280xp_resources = { > .link_entities = camss_link_entities > }; > > +static const struct camss_resources sc7280_resources = { > + .version = CAMSS_7280, > + .pd_name = "top", > + .csiphy_res = csiphy_res_7280, > + .csid_res = csid_res_7280, > + .vfe_res = vfe_res_7280, > + .icc_res = icc_res_sc7280, > + .icc_path_num = ARRAY_SIZE(icc_res_sc7280), > + .csiphy_num = ARRAY_SIZE(csiphy_res_7280), > + .csid_num = ARRAY_SIZE(csid_res_7280), > + .vfe_num = ARRAY_SIZE(vfe_res_7280), > + .link_entities = camss_link_entities > +}; > + > static const struct of_device_id camss_dt_match[] = { > { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, > { .compatible = "qcom,msm8953-camss", .data = &msm8953_resources }, > { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, > + { .compatible = "qcom,sc7280-camss", .data = &sc7280_resources }, > { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, > { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, > { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, > diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h > index ffce0a0edbc5..9a046eea334f 100644 > --- a/drivers/media/platform/qcom/camss/camss.h > +++ b/drivers/media/platform/qcom/camss/camss.h > @@ -78,6 +78,7 @@ enum pm_domain { > > enum camss_version { > CAMSS_660, > + CAMSS_7280, > CAMSS_8x16, > CAMSS_8x53, > CAMSS_8x96,
On 12/6/2024 1:21 PM, Luca Weiss wrote: > On Wed Dec 4, 2024 at 11:00 AM CET, Vikram Sharma wrote: >> From: Suresh Vankadara <quic_svankada@quicinc.com> >> >> Add support for the camss driver on the sc7280 soc. >> >> Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> >> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> >> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> >> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> > Hi Vikram, > > This is working on QCM6490 Fairphone 5 smartphone with WIP drivers for > IMX858 and S5KJN1, thanks! > > Tested-by: Luca Weiss <luca.weiss@fairphone.com> # qcm6490-fairphone-fp5 > > Regards > Luca Hi Luca, Thanks for your help in testing this on 2 different sensors. I have posted V8 for this adding "Tested-by" tag with your name. Best Regards, Vikram > >> --- >> .../qcom/camss/camss-csiphy-3ph-1-0.c | 5 + >> .../media/platform/qcom/camss/camss-csiphy.c | 5 + >> .../media/platform/qcom/camss/camss-csiphy.h | 1 + >> drivers/media/platform/qcom/camss/camss-vfe.c | 2 + >> drivers/media/platform/qcom/camss/camss.c | 319 ++++++++++++++++++ >> drivers/media/platform/qcom/camss/camss.h | 1 + >> 6 files changed, 333 insertions(+) >> >> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c >> index 7d2490c9de01..f341f7b7fd8a 100644 >> --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c >> +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c >> @@ -505,6 +505,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, >> u32 val; >> >> switch (csiphy->camss->res->version) { >> + case CAMSS_7280: >> + r = &lane_regs_sm8250[0][0]; >> + array_size = ARRAY_SIZE(lane_regs_sm8250[0]); >> + break; >> case CAMSS_8250: >> r = &lane_regs_sm8250[0][0]; >> array_size = ARRAY_SIZE(lane_regs_sm8250[0]); >> @@ -557,6 +561,7 @@ static bool csiphy_is_gen2(u32 version) >> bool ret = false; >> >> switch (version) { >> + case CAMSS_7280: >> case CAMSS_8250: >> case CAMSS_8280XP: >> case CAMSS_845: >> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c >> index 5af2b382a843..3791c2d8a6cf 100644 >> --- a/drivers/media/platform/qcom/camss/camss-csiphy.c >> +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c >> @@ -103,6 +103,11 @@ const struct csiphy_formats csiphy_formats_8x96 = { >> .formats = formats_8x96 >> }; >> >> +const struct csiphy_formats csiphy_formats_sc7280 = { >> + .nformats = ARRAY_SIZE(formats_sdm845), >> + .formats = formats_sdm845 >> +}; >> + >> const struct csiphy_formats csiphy_formats_sdm845 = { >> .nformats = ARRAY_SIZE(formats_sdm845), >> .formats = formats_sdm845 >> diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h >> index eebc1ff1cfab..b6209bddfb61 100644 >> --- a/drivers/media/platform/qcom/camss/camss-csiphy.h >> +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h >> @@ -111,6 +111,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy); >> >> extern const struct csiphy_formats csiphy_formats_8x16; >> extern const struct csiphy_formats csiphy_formats_8x96; >> +extern const struct csiphy_formats csiphy_formats_sc7280; >> extern const struct csiphy_formats csiphy_formats_sdm845; >> >> extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0; >> diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c >> index fb3234c65403..95f6a1ac7eaf 100644 >> --- a/drivers/media/platform/qcom/camss/camss-vfe.c >> +++ b/drivers/media/platform/qcom/camss/camss-vfe.c >> @@ -335,6 +335,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, >> } >> break; >> case CAMSS_660: >> + case CAMSS_7280: >> case CAMSS_8x96: >> case CAMSS_8250: >> case CAMSS_8280XP: >> @@ -1693,6 +1694,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) >> int ret = 8; >> >> switch (vfe->camss->res->version) { >> + case CAMSS_7280: >> case CAMSS_8250: >> case CAMSS_8280XP: >> case CAMSS_845: >> diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c >> index f5704c23766a..4fa16ff6e614 100644 >> --- a/drivers/media/platform/qcom/camss/camss.c >> +++ b/drivers/media/platform/qcom/camss/camss.c >> @@ -1266,6 +1266,310 @@ static const struct resources_icc icc_res_sm8250[] = { >> }, >> }; >> >> +static const struct camss_subdev_resources csiphy_res_7280[] = { >> + /* CSIPHY0 */ >> + { >> + .regulators = { "vdda-phy", "vdda-pll" }, >> + >> + .clock = { "csiphy0", "csiphy0_timer" }, >> + .clock_rate = { { 300000000, 400000000 }, >> + { 300000000 } }, >> + .reg = { "csiphy0" }, >> + .interrupt = { "csiphy0" }, >> + .csiphy = { >> + .hw_ops = &csiphy_ops_3ph_1_0, >> + .formats = &csiphy_formats_sc7280 >> + } >> + }, >> + /* CSIPHY1 */ >> + { >> + .regulators = { "vdda-phy", "vdda-pll" }, >> + >> + .clock = { "csiphy1", "csiphy1_timer" }, >> + .clock_rate = { { 300000000, 400000000 }, >> + { 300000000 } }, >> + .reg = { "csiphy1" }, >> + .interrupt = { "csiphy1" }, >> + .csiphy = { >> + .hw_ops = &csiphy_ops_3ph_1_0, >> + .formats = &csiphy_formats_sc7280 >> + } >> + }, >> + /* CSIPHY2 */ >> + { >> + .regulators = { "vdda-phy", "vdda-pll" }, >> + >> + .clock = { "csiphy2", "csiphy2_timer" }, >> + .clock_rate = { { 300000000, 400000000 }, >> + { 300000000 } }, >> + .reg = { "csiphy2" }, >> + .interrupt = { "csiphy2" }, >> + .csiphy = { >> + .hw_ops = &csiphy_ops_3ph_1_0, >> + .formats = &csiphy_formats_sc7280 >> + } >> + }, >> + /* CSIPHY3 */ >> + { >> + .regulators = { "vdda-phy", "vdda-pll" }, >> + >> + .clock = { "csiphy3", "csiphy3_timer" }, >> + .clock_rate = { { 300000000, 400000000 }, >> + { 300000000 } }, >> + .reg = { "csiphy3" }, >> + .interrupt = { "csiphy3" }, >> + .csiphy = { >> + .hw_ops = &csiphy_ops_3ph_1_0, >> + .formats = &csiphy_formats_sc7280 >> + } >> + }, >> + /* CSIPHY4 */ >> + { >> + .regulators = { "vdda-phy", "vdda-pll" }, >> + >> + .clock = { "csiphy4", "csiphy4_timer" }, >> + .clock_rate = { { 300000000, 400000000 }, >> + { 300000000 } }, >> + .reg = { "csiphy4" }, >> + .interrupt = { "csiphy4" }, >> + .csiphy = { >> + .hw_ops = &csiphy_ops_3ph_1_0, >> + .formats = &csiphy_formats_sc7280 >> + } >> + }, >> +}; >> + >> +static const struct camss_subdev_resources csid_res_7280[] = { >> + /* CSID0 */ >> + { >> + .regulators = {}, >> + >> + .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0" }, >> + .clock_rate = { { 300000000, 400000000 }, >> + { 0 }, >> + { 380000000, 510000000, 637000000, 760000000 } >> + }, >> + >> + .reg = { "csid0" }, >> + .interrupt = { "csid0" }, >> + .csid = { >> + .is_lite = false, >> + .hw_ops = &csid_ops_gen2, >> + .parent_dev_ops = &vfe_parent_dev_ops, >> + .formats = &csid_formats_gen2 >> + } >> + }, >> + /* CSID1 */ >> + { >> + .regulators = {}, >> + >> + .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1" }, >> + .clock_rate = { { 300000000, 400000000 }, >> + { 0 }, >> + { 380000000, 510000000, 637000000, 760000000 } >> + }, >> + >> + .reg = { "csid1" }, >> + .interrupt = { "csid1" }, >> + .csid = { >> + .is_lite = false, >> + .hw_ops = &csid_ops_gen2, >> + .parent_dev_ops = &vfe_parent_dev_ops, >> + .formats = &csid_formats_gen2 >> + } >> + }, >> + /* CSID2 */ >> + { >> + .regulators = {}, >> + >> + .clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2" }, >> + .clock_rate = { { 300000000, 400000000 }, >> + { 0 }, >> + { 380000000, 510000000, 637000000, 760000000 } >> + }, >> + >> + .reg = { "csid2" }, >> + .interrupt = { "csid2" }, >> + .csid = { >> + .is_lite = false, >> + .hw_ops = &csid_ops_gen2, >> + .parent_dev_ops = &vfe_parent_dev_ops, >> + .formats = &csid_formats_gen2 >> + } >> + }, >> + /* CSID3 */ >> + { >> + .regulators = {}, >> + >> + .clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" }, >> + .clock_rate = { { 300000000, 400000000 }, >> + { 0 }, >> + { 320000000, 400000000, 480000000, 600000000 } >> + }, >> + >> + .reg = { "csid_lite0" }, >> + .interrupt = { "csid_lite0" }, >> + .csid = { >> + .is_lite = true, >> + .hw_ops = &csid_ops_gen2, >> + .parent_dev_ops = &vfe_parent_dev_ops, >> + .formats = &csid_formats_gen2 >> + } >> + }, >> + /* CSID4 */ >> + { >> + .regulators = {}, >> + >> + .clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" }, >> + .clock_rate = { { 300000000, 400000000 }, >> + { 0 }, >> + { 320000000, 400000000, 480000000, 600000000 } >> + }, >> + >> + .reg = { "csid_lite1" }, >> + .interrupt = { "csid_lite1" }, >> + .csid = { >> + .is_lite = true, >> + .hw_ops = &csid_ops_gen2, >> + .parent_dev_ops = &vfe_parent_dev_ops, >> + .formats = &csid_formats_gen2 >> + } >> + }, >> +}; >> + >> +static const struct camss_subdev_resources vfe_res_7280[] = { >> + /* VFE0 */ >> + { >> + .regulators = {}, >> + >> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe0", >> + "vfe0_axi", "gcc_cam_hf_axi" }, >> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, >> + { 80000000 }, >> + { 0 }, >> + { 380000000, 510000000, 637000000, 760000000 }, >> + { 0 }, >> + { 0 } }, >> + >> + .reg = { "vfe0" }, >> + .interrupt = { "vfe0" }, >> + .vfe = { >> + .line_num = 3, >> + .is_lite = false, >> + .has_pd = true, >> + .pd_name = "ife0", >> + .hw_ops = &vfe_ops_170, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE1 */ >> + { >> + .regulators = {}, >> + >> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe1", >> + "vfe1_axi", "gcc_cam_hf_axi" }, >> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, >> + { 80000000 }, >> + { 0 }, >> + { 380000000, 510000000, 637000000, 760000000 }, >> + { 0 }, >> + { 0 } }, >> + >> + .reg = { "vfe1" }, >> + .interrupt = { "vfe1" }, >> + .vfe = { >> + .line_num = 3, >> + .is_lite = false, >> + .has_pd = true, >> + .pd_name = "ife1", >> + .hw_ops = &vfe_ops_170, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE2 */ >> + { >> + .regulators = {}, >> + >> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", "vfe2", >> + "vfe2_axi", "gcc_cam_hf_axi" }, >> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, >> + { 80000000 }, >> + { 0 }, >> + { 380000000, 510000000, 637000000, 760000000 }, >> + { 0 }, >> + { 0 } }, >> + >> + .reg = { "vfe2" }, >> + .interrupt = { "vfe2" }, >> + .vfe = { >> + .line_num = 3, >> + .is_lite = false, >> + .hw_ops = &vfe_ops_170, >> + .has_pd = true, >> + .pd_name = "ife2", >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE3 (lite) */ >> + { >> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", >> + "vfe_lite0", "gcc_cam_hf_axi" }, >> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, >> + { 80000000 }, >> + { 0 }, >> + { 320000000, 400000000, 480000000, 600000000 }, >> + { 0 } }, >> + >> + .regulators = {}, >> + .reg = { "vfe_lite0" }, >> + .interrupt = { "vfe_lite0" }, >> + .vfe = { >> + .line_num = 4, >> + .is_lite = true, >> + .hw_ops = &vfe_ops_170, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> + /* VFE4 (lite) */ >> + { >> + .clock = { "camnoc_axi", "cpas_ahb", "icp_ahb", >> + "vfe_lite1", "gcc_cam_hf_axi" }, >> + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, >> + { 80000000 }, >> + { 0 }, >> + { 320000000, 400000000, 480000000, 600000000 }, >> + { 0 } }, >> + >> + .regulators = {}, >> + .reg = { "vfe_lite1" }, >> + .interrupt = { "vfe_lite1" }, >> + .vfe = { >> + .line_num = 4, >> + .is_lite = true, >> + .hw_ops = &vfe_ops_170, >> + .formats_rdi = &vfe_formats_rdi_845, >> + .formats_pix = &vfe_formats_pix_845 >> + } >> + }, >> +}; >> + >> +static const struct resources_icc icc_res_sc7280[] = { >> + { >> + .name = "ahb", >> + .icc_bw_tbl.avg = 38400, >> + .icc_bw_tbl.peak = 76800, >> + }, >> + { >> + .name = "hf_0", >> + .icc_bw_tbl.avg = 2097152, >> + .icc_bw_tbl.peak = 2097152, >> + }, >> +}; >> + >> static const struct camss_subdev_resources csiphy_res_sc8280xp[] = { >> /* CSIPHY0 */ >> { >> @@ -2622,10 +2926,25 @@ static const struct camss_resources sc8280xp_resources = { >> .link_entities = camss_link_entities >> }; >> >> +static const struct camss_resources sc7280_resources = { >> + .version = CAMSS_7280, >> + .pd_name = "top", >> + .csiphy_res = csiphy_res_7280, >> + .csid_res = csid_res_7280, >> + .vfe_res = vfe_res_7280, >> + .icc_res = icc_res_sc7280, >> + .icc_path_num = ARRAY_SIZE(icc_res_sc7280), >> + .csiphy_num = ARRAY_SIZE(csiphy_res_7280), >> + .csid_num = ARRAY_SIZE(csid_res_7280), >> + .vfe_num = ARRAY_SIZE(vfe_res_7280), >> + .link_entities = camss_link_entities >> +}; >> + >> static const struct of_device_id camss_dt_match[] = { >> { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, >> { .compatible = "qcom,msm8953-camss", .data = &msm8953_resources }, >> { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, >> + { .compatible = "qcom,sc7280-camss", .data = &sc7280_resources }, >> { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, >> { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, >> { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, >> diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h >> index ffce0a0edbc5..9a046eea334f 100644 >> --- a/drivers/media/platform/qcom/camss/camss.h >> +++ b/drivers/media/platform/qcom/camss/camss.h >> @@ -78,6 +78,7 @@ enum pm_domain { >> >> enum camss_version { >> CAMSS_660, >> + CAMSS_7280, >> CAMSS_8x16, >> CAMSS_8x53, >> CAMSS_8x96,
SC7280 is a Qualcomm SoC. This series adds support to bring up the CSIPHY, CSID, VFE/RDI interfaces in SC7280. SC7280 provides - 3 x VFE, 3 RDI per VFE - 2 x VFE Lite, 4 RDI per VFE - 3 x CSID - 2 x CSID Lite - 5 x CSI PHY The changes are verified on SC7280 qcs6490-rb3gen2 board, with attached vision mezzanine TPG (mode 1-9) and IMX577 sensor. The base dts for qcs6490-rb3gen2 is: https://lore.kernel.org/all/20231103184655.23555-1-quic_kbajaj@quicinc.com/ This change is dependent on below series. As it is raised on top of this. Please take both to validate. https://lore.kernel.org/lkml/20241126100126.2743795-1-quic_vikramsa@quicinc.com/ Used following tools for the sanity check of these changes. - make CHECK_DTBS=y W=1 DT_SCHEMA_FILES=media/qcom,sc7280-camss.yaml qcom/qcs6490-rb3gen2-vision-mezzanine.dtb - make DT_CHECKER_FLAGS=-m W=1 DT_SCHEMA_FILES=media/qcom,sc7280-camss.yaml dt_binding_check - Smatch: make CHECK="smatch --full-path" M=drivers/media/platform/qcom/camss/ - Sparse: make C=2 M=drivers/media/platform/qcom/camss/ - coccicheck : make coccicheck M=drivers/media/platform/qcom/camss/ - make -j32 W=1 - ./scripts/checkpatch.pl Changes in V7: - Changed unit address for camss in documention and dts. - Added avdd-supply and dvdd-supply for sensor. - Changed reg/clocks/interrupts name for vfe_lite and csid_lite. - Link to v6: https://lore.kernel.org/linux-arm-msm/20241127100421.3447601-1-quic_vikramsa@quicinc.com/ Changes in V6: - Changed order of properties in Documentation [PATCH 1/5]. - Updated description for ports in Documentaion [PATCH 1/5]. - Moved regulators from csid to csiphy [PATCH 3/5]. - Link to v5: https://lore.kernel.org/linux-arm-msm/20241112173032.2740119-1-quic_vikramsa@quicinc.com/ Changes in V5: - Updated Commit text for [PATCH v5 1/6]. - Moved reg after compatible string. - Renamed csi'x' clocks to vfe'x'_csid - Removed [PATCH v4 4/6] and raised a seprate series for this one. - Moved gpio states to mezzanine dtso. - Added more clock levels to address TPG related issues. - Renamed power-domains-names -> power-domain-names. - Link to v4: https://lore.kernel.org/linux-arm-msm/20241030105347.2117034-1-quic_vikramsa@quicinc.com/ Changes in V4: - V3 had 8 patches and V4 is reduced to 6. - Removed [Patch v3 2/8] as binding change is not required for dtso. - Removed [Patch v3 3/8] as the fix is already taken care in latest kernel tip. - Updated alignment for dtsi and dt-bindings. - Adding qcs6490-rb3gen2-vision-mezzanine as overlay. - Link to v3: https://lore.kernel.org/linux-arm-msm/20241011140932.1744124-1-quic_vikramsa@quicinc.com/ Changes in V3: - Added missed subject line for cover letter of V2. - Updated Alignment, indentation and properties order. - edit commit text for [PATCH 02/10] and [PATCH 03/10]. - Refactor camss_link_entities. - Removed camcc enablement changes as it already done. - Link to v2: https://lore.kernel.org/linux-arm-msm/20240904-camss_on_sc7280_rb3gen2_vision_v2_patches-v1-0-b18ddcd7d9df@quicinc.com/ Changes in V2: - Improved indentation/formatting. - Removed _src clocks and misleading code comments. - Added name fields for power domains and csid register offset in DTSI. - Dropped minItems field from YAML file. - Listed changes in alphabetical order. - Updated description and commit text to reflect changes - Changed the compatible string from imx412 to imx577. - Added board-specific enablement changes in the newly created vision board DTSI file. - Fixed bug encountered during testing. - Moved logically independent changes to a new/seprate patch. - Removed cci0 as no sensor is on this port and MCLK2, which was a copy-paste error from the RB5 board reference. - Added power rails, referencing the RB5 board. - Discarded Patch 5/6 completely (not required). - Removed unused enums. - Link to v1: https://lore.kernel.org/linux-arm-msm/20240629-camss_first_post_linux_next-v1-0-bc798edabc3a@quicinc.com/ Suresh Vankadara (1): media: qcom: camss: Add support for camss driver on sc7280 Vikram Sharma (4): media: dt-bindings: Add qcom,sc7280-camss media: qcom: camss: Sort camss version enums and compatible strings arm64: dts: qcom: sc7280: Add support for camss arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine .../bindings/media/qcom,sc7280-camss.yaml | 418 ++++++++++++++++++ arch/arm64/boot/dts/qcom/Makefile | 4 + .../qcs6490-rb3gen2-vision-mezzanine.dtso | 110 +++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 172 +++++++ .../qcom/camss/camss-csiphy-3ph-1-0.c | 13 +- .../media/platform/qcom/camss/camss-csiphy.c | 5 + .../media/platform/qcom/camss/camss-csiphy.h | 1 + drivers/media/platform/qcom/camss/camss-vfe.c | 8 +- drivers/media/platform/qcom/camss/camss.c | 321 +++++++++++++- drivers/media/platform/qcom/camss/camss.h | 5 +- 10 files changed, 1047 insertions(+), 10 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso