Message ID | 20210608104128.1616028-1-martin.kepplinger@puri.sm |
---|---|
Headers | show |
Series | media: imx: add support for imx8mq MIPI RX | expand |
Hi Martin, On 21-06-08 12:41, Martin Kepplinger wrote: ... > + csi1: csi@30a90000 { > + compatible = "fsl,imx7-csi"; AFAIK an unwritten rule (at least for the iMX mach) is to specify the SoC specific compatible and the compatible which is supported by the driver already, so this should be: compatible = "fsl,imx8mq-csi", "fsl,imx7-csi"; This is very helpful if we need to handle some quirk for the imx8mq later on. Regards, Marco > + reg = <0x30a90000 0x10000>; > + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; > + clock-names = "mclk"; > + status = "disabled"; > + > + port { > + csi1_ep: endpoint { > + remote-endpoint = <&csi1_mipi_ep>; > + }; > + }; > + }; > + > + mipi_csi2: csi@30b60000 { > + compatible = "fsl,imx8mq-mipi-csi2"; > + reg = <0x30b60000 0x1000>; > + clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, > + <&clk IMX8MQ_CLK_CSI2_ESC>, > + <&clk IMX8MQ_CLK_CSI2_PHY_REF>, > + <&clk IMX8MQ_CLK_CLKO2>; > + clock-names = "core", "esc", "pxl", "clko2"; > + assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, > + <&clk IMX8MQ_CLK_CSI2_PHY_REF>, > + <&clk IMX8MQ_CLK_CSI2_ESC>; > + assigned-clock-rates = <266000000>, <333000000>, <66000000>; > + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, > + <&clk IMX8MQ_SYS2_PLL_1000M>, > + <&clk IMX8MQ_SYS1_PLL_800M>; > + power-domains = <&pgc_mipi_csi2>; > + reset = <&src>; > + phy = <&iomuxc_gpr>; > + interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>; > + interconnect-names = "dram"; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + csi2_mipi_ep: endpoint { > + remote-endpoint = <&csi2_ep>; > + }; > + }; > + }; > + }; > + > + csi2: csi@30b80000 { > + compatible = "fsl,imx7-csi"; > + reg = <0x30b80000 0x10000>; > + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; > + clock-names = "mclk"; > + status = "disabled"; > + > + port { > + csi2_ep: endpoint { > + remote-endpoint = <&csi2_mipi_ep>; > + }; > + }; > + }; > + > mu: mailbox@30aa0000 { > compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; > reg = <0x30aa0000 0x10000>; > -- > 2.30.2 > > > _______________________________________________ > linux-arm-kernel mailing list > linux-arm-kernel@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >
On Tue, Jun 08, 2021 at 12:41:26PM +0200, Martin Kepplinger wrote: > The i.MX8MQ SoC integrates a different MIPI CSI receiver as the i.MX8MM so > describe the DT bindings for it. > > Signed-off-by: Martin Kepplinger <martin.kepplinger@puri.sm> > --- > .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 161 ++++++++++++++++++ > 1 file changed, 161 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > > diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > new file mode 100644 > index 000000000000..6eafdf803d36 > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml > @@ -0,0 +1,161 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NXP i.MX8MQ MIPI CSI-2 receiver > + > +maintainers: > + - Martin Kepplinger <martin.kepplinger@puri.sm> > + > +description: |- > + This binding covers the CSI-2 RX PHY and host controller included in the > + NXP i.MX8MQ SoC. It handles the sensor/image input and process for all the > + input imaging devices. > + > +properties: > + compatible: > + enum: > + - fsl,imx8mq-mipi-csi2 > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: core is the RX Controller Core Clock input. This clock > + must be exactly equal to or faster than the receive > + byteclock from the RX DPHY. > + - description: esc is the Rx Escape Clock. This must be the same escape > + clock that the RX DPHY receives. > + - description: pxl is the pixel clock (phy_ref up to 333Mhz). > + - description: clko2 is the CLKO2 clock root. > + See the reference manual for details. > + > + clock-names: > + items: > + - const: core > + - const: esc > + - const: pxl > + - const: clko2 > + > + power-domains: > + maxItems: 1 > + > + reset: resets > + description: > + The phandle to the imx8mq reset-controller. Drop. What the reset controller is is out of scope for a binding. > + maxItems: 1 > + > + phy: phys? Assuming this is using the PHY binding. If it is not, then why not? > + description: > + The phandle to the imx8mq syscon iomux-gpr. > + maxItems: 1 > + > + interconnects: > + maxItems: 1 > + > + interconnect-names: > + const: dram > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port node, single endpoint describing the CSI-2 transmitter. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + items: > + minItems: 1 > + maxItems: 4 > + items: > + - const: 1 > + - const: 2 > + - const: 3 > + - const: 4 > + > + required: > + - data-lanes > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output port node > + > + required: > + - port@0 > + - port@1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - power-domains > + - reset > + - phy > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/imx8mq-clock.h> > + #include <dt-bindings/interconnect/imx8mq.h> > + > + csi@30a70000 { > + compatible = "fsl,imx8mq-mipi-csi2"; > + reg = <0x30a70000 0x1000>; > + clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, > + <&clk IMX8MQ_CLK_CSI1_ESC>, > + <&clk IMX8MQ_CLK_CSI1_PHY_REF>, > + <&clk IMX8MQ_CLK_CLKO2>; > + clock-names = "core", "esc", "pxl", "clko2"; > + assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, > + <&clk IMX8MQ_CLK_CSI1_PHY_REF>, > + <&clk IMX8MQ_CLK_CSI1_ESC>; > + assigned-clock-rates = <266000000>, <200000000>, <66000000>; > + assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, > + <&clk IMX8MQ_SYS2_PLL_1000M>, > + <&clk IMX8MQ_SYS1_PLL_800M>; > + power-domains = <&pgc_mipi_csi1>; > + reset = <&src>; > + phy = <&iomuxc_gpr>; > + interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>; > + interconnect-names = "dram"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + imx8mm_mipi_csi_in: endpoint { > + remote-endpoint = <&imx477_out>; > + data-lanes = <1 2 3 4>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + imx8mm_mipi_csi_out: endpoint { > + remote-endpoint = <&csi_in>; > + }; > + }; > + }; > + }; > + > +... > -- > 2.30.2